MPC8569E datasheet(35/127 Pages) FREESCALE

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Pinout List

MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

XGND

U24

SerDes Transceiver

Pad GND

——

XGND

V22

SerDes Transceiver

Pad GND

——

XGND

W23

SerDes Transceiver

Pad GND

——

XGND

Y21

SerDes Transceiver

Pad GND

——

AGND_SRDS

U25

SerDes PLL GND

—

Notes:

1. All multiplexed signals are listed only once and do not reoccur.

2. This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the processor is in the

reset state. This pull-up is designed such that it can be overpowered by an external 4.7-k

Ω pull-down resistor. However, if the

signal is intended to be high after reset, and if there is any device on the net which might pull down the value of the net at

reset, then a pull-up or active driver is needed.

3. When configured as I2C, this pin is an open drain signal and recommend a pull-up resistor (1 k

Ω) be placed on this pin to

OVDD. When configured as SD, this pin is not open drain and does not require a pull-up.

4. This pin has a weak internal pull-up resistor (~20 k

Ω).

5. This pin is an open drain signal.

6. Recommend a weak pull-up resistor (2–10 k

Ω) be placed on this pin to OV

DD.

7. This pin requires a 200-

Ω pull-down to ground.

8. Do not connect.

9. Recommend a weak pull-down resistor (2–10 k

Ω) be placed on this pin to GND.

10. These are test signals for factory use only and must be pulled up (100

Ω–1 kΩ) to OV

DD for normal machine operation.

11. These pins must not be pulled down during power-on reset.

12. See AN4232 MPC8569E PowerQUICC III Design Checklist for the required PLL filters to be attached to the AVDD pin.

13. These pins are connected to the VDD/GND planes internally and may be used by the core power supply to improve tracking

and regulation.

14. This pin selects the voltage of eLBC interface (BVDD). This pin has internal weak pull down.

15. This pin selects the voltage of UCC1 and UCC3 interfaces (LVDD1). This pin has internal weak pull down.

16. This pin selects the voltage of UCC2 and UCC4 interfaces (LVDD2). This pin has internal weak pull down.

17. This pin requires a 100-

Ω pull down to ground.

18. The value of LA[24:27] during reset sets the CCB clock to SYSCLK PLL ratio. These pins require 4.7-k

Ω pull-up or pull-down

resistors. See AN4232 MPC8569E PowerQUICC III Design Checklist for more details.

19. The value of QE_PE[27:29] during reset sets the DDR clock PLL settings. These pins require 4.7-k

Ω pull up or pull down

resistors. See AN4232 MPC8569E PowerQUICC III Design Checklist for more details.

20. The value of LALE, LGPL2/LOE/LFRE and LBCTL at reset set the e500 core clock to CCB Clock PLL ratio. These pins

require 4.7-k

Ω pull-up or pull-down resistors. See the AN4232 MPC8569E PowerQUICC III Design Checklist for more details.

21. The value of LCS[3:7] at reset sets the QE PLL settings. These pins require 4.7-k

Ω pull up or pull down resistors. See

AN4232 MPC8569E PowerQUICC III Design Checklist for more details.

22. The value of QE_PB[27:28], QE_PC4 and QE_PD4 at reset sets the Boot ROM location. These pins require 4.7-k

Ω pull up

or pull down resistors. See the MPC8569E PowerQUICC III Integrated Host Processor Family Reference Manual for details

23. These pins are sampled at reset for general-purpose configuration use by software. The value of LAD[0:15] at reset sets the

upper 16 bits of the GPPORCR

24. These pins must not be pulled up during power-on reset.

25. This output is actively driven during reset rather than being three-stated during reset.

Table 1. MPC8569E Pinout Listing (continued)

Signal1

Package Pin Number

Pin Type

Power Supply

Note

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