MPC8569E datasheet(113/127 Pages) FREESCALE

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SPI Interface

MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

113

The following figure provides the AC test load for the SPI.

Figure 64. SPI AC Test Load

Figure 65 and Figure 66 represent the AC timing from Table 75. Note that although the specifications generally reference the

rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge.

The following figure shows the SPI timing in slave mode (external clock).

Figure 65. SPI AC Timing in Slave Mode (External Clock) Diagram

SPI inputs—Master mode (internal clock) input setup time

tNIIVKH

4—

—

SPI inputs—Master mode (internal clock) input hold time

tNIIXKH

0—

—

SPI inputs—Slave mode (external clock) input setup time

tNEIVKH

4—

—

SPI inputs—Slave mode (external clock) input hold time

tNEIXKH

2—

—

Note:

1 The symbols used for timing specifications follow the pattern of t

(first two letters of functional block)(signal)(state) (reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOX symbolizes the internal

timing (NI) for the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X).

2. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are

measured at the pin.

Table 75. SPI AC Timing Specifications (continued)

For recommended operating conditions, see Table 3

Parameter

Symbol1

Min

Max

Unit

Note

Output

Z0 = 50 Ω

OVDD/2

RL = 50 Ω

SPICLK (output)

tNEIXKH

tNEKHOV

Input Signals:

SPIMISO

(See Note)

Output Signals:

SPIMOSI

(See Note)

tNEIVKH

tNEKHOX

Note: The clock edge is selectable on SPI.

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