MPC8569E datasheet(78/127 Pages) FREESCALE

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MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

High-Speed SerDes Interfaces (HSSI)

Freescale Semiconductor

Figure 36 and Figure 37 represent the AC timing from Table 45 and Table 46. Note that although the specifications generally

refer to the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. Also note

that the clock edge is selectable.

The following figure shows the timing with external clock.

Figure 36. AC Timing (External Clock) Diagram

The following figure shows the timing with internal clock.

Figure 37. AC Timing (Internal Clock) Diagram

2.9

High-Speed SerDes Interfaces (HSSI)

The MPC859E features a serializer/deserializer (SerDes) interface to be used for high-speed serial interconnect

applications.The SerDes interface can be used for PCI Express and/or Serial RapidIO and/or SGMII data transfers.

This section describes the common portion of SerDes DC electrical specifications, which is the DC requirement for SerDes

reference clocks. The SerDes data lane’s transmitter (Tx) and receiver (Rx) reference circuits are also shown.

2.9.1

Signal Terms Definition

The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms used in the description

and specification of differential signals.

The below figure shows how the signals are defined. For illustration purposes only, one SerDes lane is used in the description.

The following figure shows the waveform for either a transmitter output (SDn_TX and SDn_TX) or a receiver input (SDn_RX

and SDn_RX). Each signal swings between A volts and B volts where A > B.

Serial CLK (Input)

tHEIXKH

tHEIVKH

tHEKHOV

tHEKHOX

Note: The clock edge is selectable.

Input Signals:

(See Note)

Output Signals:

(See Note)

Serial CLK (Output)

tHIIXKH

tHIKHOV

Input Signals:

Output Signals:

tHIIVKH

tHIKHOX

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