MPC8569E datasheet(115/127 Pages) FREESCALE

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TDM/SI

MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

115

The following figure provides the AC test load for the TDM/SI.

Figure 67. TDM/SI AC Test Load

The below figure represents the AC timing from Table 77. Note that although the specifications generally reference the rising

edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. The following figure shows

the TDM/SI timing with external clock.

Figure 68. TDM/SI AC Timing (External Clock) Diagram

Table 77. TDM/SI AC Timing Specifications1

Characteristic

Symbol2

Min

Max

Unit

TDM/SI outputs—External clock delay

tSEKHOV

211

TDM/SI outputs—External clock High Impedance

tSEKHOX

210

TDM/SI inputs—External clock input setup time

tSEIVKH

5—

TDM/SI inputs—External clock input hold time

tSEIXKH

2—

Notes:

1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are

measured at the pin.

2. The symbols used for timing specifications follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for inputs

and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tSEKHOX symbolizes the TDM/SI outputs

external timing (SE) for the time tTDM/SI memory clock reference (K) goes from the high state (H) until outputs (O) are invalid

(X).

Output

Z0 = 50 Ω

OVDD/2

RL = 50 Ω

TDM/SICLK (Input)

tSEIXKH

tSEIVKH

tSEKHOV

Input Signals:

TDM/SI

(See Note)

Output Signals:

TDM/SI

(See Note)

tSEKHOX

Note: The clock edge is selectable on TDM/SI.

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