MPC8569E datasheet(92/127 Pages) FREESCALE

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MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Serial RapidIO (SRIO)

Freescale Semiconductor

2.11.3

DC Requirements for Serial RapidIO

This section explains the DC requirements for the Serial RapidIO interface.

2.11.3.1

DC Requirements for Serial RapidIO SD_REF_CLK and SD_REF_CLK

The characteristics and DC requirements of the separate SerDes reference clocks of the SRIO interface are described in

Section 2.9.2.3, “DC Level Requirement for SerDes Reference Clocks.”

2.11.3.2

DC Serial RapidIO Timing Transmitter Specifications

The LP-serial transmitter electrical and timing specifications are given in the following sections.

The differential return loss, S11, of the transmitter in each case are better than the following:

•

–10 dB for (Baud Frequency)

÷ 10 < Freq(f) < 625 MHz

•

–10 dB + 10log(f

÷ 625 MHz) dB for 625 MHz ≤ Freq(f) ≤ Baud Frequency

The reference impedance for the differential return loss measurements is 100-

Ω resistive. Differential return loss includes

contributions from on-chip circuitry, chip packaging, and any off-chip components related to the driver. The output impedance

requirement applies to all valid output levels.

It is recommended that the 20%–80% rise/fall time of the transmitter, as measured at the transmitter output, in each case have

a minimum value 60 ps.

It is recommended that the timing skew at the output of an LP-serial transmitter between the two signals that comprise a

differential pair not exceed 25 ps at 1.25 GB, 20 ps at 2.50 GB, and 15 ps at 3.125 GB.

The following table defines the serial RapidIO transmitter DC specifications.

2.11.3.3

DC Serial RapidIO Receiver Specifications

The LP-serial receiver electrical and timing specifications are given in the following sections.

Receiver input impedance shall result in a differential return loss better that 10 dB and a common mode return loss better than

6 dB from 100 MHz to (0.8)

× (baud frequency). This includes contributions from on-chip circuitry, the chip package, and any

off-chip components related to the receiver. AC coupling components are included in this requirement. The reference

impedance for return loss measurements is 100-

Ω resistive for differential return loss and 25-Ω resistive for common mode.

Table 53. SRIO Transmitter DC Timing Specifications—1.25, 2.5, and 3.125 GBauds

At recommended operating conditions with XVDD = 1.0 V ± 3%. and 1.1 V ± 3%

Parameter

Symbol

Min

Typ

Max

Unit

Notes

Output voltage

–0.40

—

2.30

Long-run differential output voltage

VDIFFPP

800

—

1600

mV p-p

—

Short-run differential output voltage

VDIFFPP

500

—

1000

mV p-p

—

Note:

1. Voltage relative to COMMON of either signal comprising a differential pair.

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