PIC18F23K22-ESLASHML datasheet(166/496 Pages) MICROCHIP

166 / 496 page

PIC18(L)F2X/4XK22

DS41412C-page 166

Preliminary

 2010 Microchip Technology Inc.

12.8

Timer1/3/5 Interrupt

The

Timer1/3/5

pair

(TMRxH:TMRxL)

increments to FFFFh and rolls over to 0000h. When

Timer1/3/5 rolls over, the Timer1/3/5 interrupt flag bit of

the PIR1/2/5 register is set. To enable the interrupt on

rollover, you must set these bits:

• TMRxON bit of the TxCON register

• TMRxIE bits of the PIE1, PIE2 or PIE5 registers

• PEIE/GIEL bit of the INTCON register

• GIE/GIEH bit of the INTCON register

The interrupt is cleared by clearing the TMRxIF bit in

the Interrupt Service Routine.

For more information on selecting high or low priority

status for the Timer1/3/5 Overflow Interrupt, see

Section 9.0 “Interrupts”.

12.9

Timer1/3/5 Operation During Sleep

Timer1/3/5 can only operate during Sleep when setup

in Asynchronous Counter mode. In this mode, an

external crystal or clock source can be used to

increment the counter. To set up the timer to wake the

device:

• TMRxON bit of the TxCON register must be set

• TMRxIE bit of the PIE1/2/5 register must be set

• PEIE/GIEL bit of the INTCON register must be set

• TxSYNC bit of the TxCON register must be set

• TMRxCS bits of the TxCON register must be

configured

• TxSOSCEN bit of the TxCON register must be

configured

The device will wake-up on an overflow and execute

the next instruction. If the GIE/GIEH bit of the INTCON

Routine.

The secondary oscillator will continue to operate in

Sleep regardless of the TxSYNC bit setting.

12.10 ECCP/CCP Capture/Compare Time

Base

The CCP modules use the TMRxH:TMRxL register pair

as the time base when operating in Capture or

Compare mode.

In Capture mode, the value in the TMRxH:TMRxL

In Compare mode, an event is triggered when the value

CCPRxH:CCPRxL register pair matches the value in

the TMRxH:TMRxL register pair. This event can be a

Special Event Trigger.

For

information,

see

Section 14.0

“Capture/Compare/PWM Modules”.

12.11 ECCP/CCP Special Event Trigger

When any of the CCP’s are configured to trigger a

special event, the trigger will clear the TMRxH:TMRxL

Timer1/3/5 interrupt. The CCP module may still be

configured to generate a CCP interrupt.

In this mode of operation, the CCPRxH:CCPRxL

Timer1/3/5.

Timer1/3/5 should be synchronized and FOSC/4 should

be selected as the clock source in order to utilize the

Special Event Trigger. Asynchronous operation of

Timer1/3/5 can cause a Special Event Trigger to be

missed.

In the event that a write to TMRxH or TMRxL coincides

with a Special Event Trigger from the CCP, the write will

take precedence.

For more information, see Section 17.2.8 “Special

Event Trigger”.

Note:

The TMRxH:TMRxL register pair and the

TMRxIF bit should be cleared before

enabling interrupts.

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