PIC18F23K22-ESLASHML datasheet(149/496 Pages) MICROCHIP

149 / 496 page

 2010 Microchip Technology Inc.

Preliminary

DS41412C-page 149

PIC18(L)F2X/4XK22

10.6

PORTE Registers

Depending on the particular PIC18(L)F2X/4XK22

device selected, PORTE is implemented in two

different ways.

10.6.1

PORTE ON 40/44-PIN DEVICES

For PIC18(L)F2X/4XK22 devices, PORTE is a 4-bit

wide port. Three pins (RE0/P3A/CCP3/AN5, RE1/P3B/

AN6 and RE2/CCP5/AN7) are individually configurable

as inputs or outputs. These pins have Schmitt Trigger

input buffers. When selected as an analog input, these

pins will read as ‘0’s.

The corresponding data direction register is TRISE.

Setting a TRISE bit (= 1) will make the corresponding

PORTE pin an input (i.e., disable the output driver).

Clearing a TRISE bit (= 0) will make the corresponding

PORTE pin an output (i.e., enable the output driver and

put the contents of the output latch on the selected pin).

TRISE controls the direction of the REx pins, even

when they are being used as analog inputs. The user

must make sure to keep the pins configured as inputs

when using them as analog inputs.

The Data Latch register (LATE) is also memory

mapped. Read-modify-write operations on the LATE

PORTE.

The fourth pin of PORTE (MCLR/VPP/RE3) is an input

only pin. Its operation is controlled by the MCLRE

Configuration bit. When selected as a port pin

(MCLRE = 0), it functions as a digital input only pin; as

such, it does not have TRIS or LAT bits associated with its

operation. Otherwise, it functions as the device’s Master

Clear input. In either configuration, RE3 also functions as

the programming voltage input during programming.

EXAMPLE 10-5:

INITIALIZING PORTE

10.6.2

PORTE ON 28-PIN DEVICES

For PIC18F2XK22 devices, PORTE is only available

when

Master

Clear

functionality

disabled

(MCLR = 0). In these cases, PORTE is a single bit,

input only port comprised of RE3 only. The pin operates

as previously described.

10.6.3

RE3 WEAK PULL-UP

The port RE3 pin has an individually controlled weak

internal pull-up. When set, the WPUE3 (TRISE<7>) bit

enables the RE3 pin pull-up. The RBPU bit of the

INTCON2 register controls pull-ups on both PORTB

and PORTE. When RBPU = 0, the weak pull-ups

become active on all pins which have the WPUE3 or

WPUBx bits set. When set, the RBPU bit disables all

weak pull-ups. The pull-ups are disabled on a Power-

on Reset. When the RE3 port pin is configured as

MCLR,

(CONFIG3H<7>,

MCLRE=1

and

CONFIG4L<2>, LVP=0), or configured for Low Voltage

Programming, (MCLRE=x and LVP=1), the pull-up is

always enabled and the WPUE3 bit has no effect.

10.6.4

PORTE OUTPUT PRIORITY

Each PORTE pin is multiplexed with other functions.

The pins, their combined functions and their output

priorities are briefly described here. For additional

information, refer to the appropriate section in this data

sheet.

When multiple outputs are enabled, the actual pin

control goes to the peripheral with the higher priority.

Table 10-4 lists the PORTE pin functions from the

highest to the lowest priority.

Analog input functions, such as ADC, comparator and

SR Latch inputs, are not shown in the priority lists.

These inputs are active when the I/O pin is set for

Analog mode using the ANSELx registers. Digital

output functions may control the pin when it is in Analog

mode with the priority shown below.

Note:

On a Power-on Reset, RE<2:0> are

configured as analog inputs.

Note:

On a Power-on Reset, RE3 is enabled as

a digital input only if Master Clear

functionality is disabled.

CLRF

PORTE

; Initialize PORTE by

; clearing output

; data latches

CLRF

LATE

; Alternate method

; to clear output

; data latches

CLRF

ANSELE ; Configure analog pins

; for digital only

MOVLW

05h

; Value used to

; initialize data

; direction

MOVWF

TRISE

; Set RE<0> as input

; RE<1> as output

; RE<2> as input

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