PIC18F23K22-ESLASHML datasheet(107/496 Pages) MICROCHIP

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Preliminary

DS41412C-page 107

PIC18(L)F2X/4XK22

7.3

Reading the Data EEPROM

Memory

To read a data memory location, the user must write the

address to the EEADR register, clear the EEPGD con-

trol bit of the EECON1 register and then set control bit,

RD. The data is available on the very next instruction

cycle; therefore, the EEDATA register can be read by

the next instruction. EEDATA will hold this value until

another read operation, or until it is written to by the

user (during a write operation).

The basic process is shown in Example 7-1.

7.4

Writing to the Data EEPROM

Memory

To write an EEPROM data location, the address must

first be written to the EEADR register and the data writ-

ten to the EEDATA register. The sequence in

Example 7-2 must be followed to initiate the write cycle.

The write will not begin if this sequence is not exactly

followed (write 55h to EECON2, write 0AAh to

EECON2, then set WR bit) for each byte. It is strongly

recommended that interrupts be disabled during this

code segment.

Additionally, the WREN bit in EECON1 must be set to

enable writes. This mechanism prevents accidental

writes to data EEPROM due to unexpected code

execution (i.e., runaway programs). The WREN bit

should be kept clear at all times, except when updating

the EEPROM. The WREN bit is not cleared by

hardware.

After a write sequence has been initiated, EECON1,

EEADR and EEDATA cannot be modified. The WR bit

will be inhibited from being set unless the WREN bit is

set. Both WR and WREN cannot be set with the same

instruction.

At the completion of the write cycle, the WR bit is

cleared by hardware and the EEPROM Interrupt Flag

bit, EEIF, is set. The user may either enable this

interrupt or poll this bit. EEIF must be cleared by

software.

7.5

Write Verify

Depending on the application, good programming

practice may dictate that the value written to the

memory should be verified against the original value.

This should be used in applications where excessive

writes can stress bits near the specification limit.

EXAMPLE 7-1:

DATA EEPROM READ

EXAMPLE 7-2:

DATA EEPROM WRITE

MOVLW

DATA_EE_ADDR

;

MOVWF

EEADR

; Data Memory Address to read

BCF

EECON1, EEPGD

; Point to DATA memory

BCF

EECON1, CFGS

; Access EEPROM

BSF

EECON1, RD

; EEPROM Read

MOVF

EEDATA, W

; W = EEDATA

MOVLW

DATA_EE_ADDR_LOW

;

MOVWF

EEADR

; Data Memory Address to write

MOVLW

DATA_EE_ADDR_HI

;

MOVWF

EEADRH

;

MOVLW

DATA_EE_DATA

;

MOVWF

EEDATA

; Data Memory Value to write

BCF

EECON1, EEPGD

; Point to DATA memory

BCF

EECON1, CFGS

; Access EEPROM

BSF

EECON1, WREN

; Enable writes

BCF

INTCON, GIE

; Disable Interrupts

MOVLW

55h

;

Required

MOVWF

EECON2

; Write 55h

Sequence

MOVLW

0AAh

;

MOVWF

EECON2

; Write 0AAh

BSF

EECON1, WR

; Set WR bit to begin write

BSF

INTCON, GIE

; Enable Interrupts

; User code execution

BCF

EECON1, WREN

; Disable writes on write complete (EEIF set)

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