MAC7200 datasheet(121/976 Pages) FREESCALE

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Detailed Signal Descriptions

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

either an open drain or push-pull pad. The pin can be configured as chip select pin PCS[5] when in Master

mode for the Serial Peripheral Interface A (DSPI_A), or as a Peripheral Chip Select Strobe to qualify the

other Chip Select signals to eliminate any decoding glitches. Each pin can be independently configured to

wake the system out of low-power mode (DOZE) when an external signal is applied using the interrupt

functionality.

4.3.20

PB[9] / PCS0 / SS[1] / NEX1MDO — Port B I/O Pin, DSPI_B and Nexus

Primary

PB[9] is a configurable general purpose input or output pin. It can be configured to provide either high or

reduced output drive, to enable or disable either a pull-up or pull-down resistor on the pin or to provide

either an open drain or push-pull pad. The pin can be configured as chip select pin PCS[0] when in Master

mode, or as slave select pin SS when in Slave mode for the Serial Peripheral Interface B (DSPI_B). After

Reset the pin is able to be used as the General purpose input or output PB9, or as a DSPI_B control line.

This pin can be configured to wake the system out of low-power mode (DOZE) when an external signal

is applied using the interrupt functionality. When the Nexus Primary Port is selected and active, this pin is

used as a Message Data Out output.

4.3.21

PB[10] / PCS[5] / PCSS — Port B I/O Pin and DSPI_B

PB[10] is a configurable general purpose input or output pin. It can be configured to provide either high

or reduced output drives, to enable or disable either a pull-up or pull-down resistors on the pin or to provide

either an open drain or push-pull pad. The pin can be configured as chip select pin PCS[5] when in Master

mode for the Serial Peripheral Interface B (DSPI_B), or as a Peripheral Chip Select Strobe to qualify the

other Chip Select signals to eliminate any decoding glitches. It can be configured to wake the system out

of low-power mode (DOZE) when an external signal is applied using the interrupt functionality.

4.3.22

PB[11] / PCS[2] / NEX1MDO — Port B I/O Pin, DSPI_B and Nexus

Primary

PB[11] is a configurable general purpose input or output pin. It can be configured to provide either high

or reduced output drives, to enable or disable either a pull-up or pull-down resistors on the pin or to provide

either an open drain or push-pull pad. The pin can be configured as a chip select pin PCS[2] when in Master

mode for the Serial Peripheral Interface B (DSPI_B). It can be configured to wake the system out of

low-power mode (DOZE) when an external signal is applied using the interrupt functionality. When the

Nexus Primary Port is selected and active, this pin is used as a Message Data Out output.

4.3.23

PB[12] / PCS[1] — Port B I/O Pin and DSPI_B

PB[12] is a configurable general purpose input or output pin. It can be configured to provide either high

or reduced output drives, to enable or disable either a pull-up or pull-down resistors on the pin or to provide

either an open drain or push-pull pad. The pins can be configured as a chip select pin PCS[1] when in

Master mode for the Serial Peripheral Interface B (DSPI_B). It can be configured to wake the system out

of low-power mode (DOZE) when an external signal is applied using the interrupt functionality.

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