MAC7200 datasheet(62/976 Pages) FREESCALE

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MAC7200 Microcontroller Family Reference Manual, Rev. 2

lxii

Freescale Semiconductor

32-11

UCCRn Field Descriptions ..................................................................................................692

32-12

ODISSL Selection................................................................................................................693

32-13

UC Internal Prescaler Clock Divider ...................................................................................693

32-14

Input Filter Bits ....................................................................................................................694

32-15

BSL Bits...............................................................................................................................695

32-16

MODE Bits ..........................................................................................................................696

32-17

UCSRn Field Descriptions...................................................................................................697

33-1

ATD External Pins ...............................................................................................................738

33-2

ATD Bus Aborts ..................................................................................................................739

33-3

DMADC1032 Signals ..........................................................................................................743

33-4

Module Memory Map ..........................................................................................................745

33-5

ATDTRIGCTL Field Descriptions ......................................................................................747

33-6

Trigger Sensitivity Selection Table .....................................................................................747

33-7

ATDETRIGCH Field Descriptions......................................................................................748

33-8

ATDPRE Field Descriptions................................................................................................749

33-9

Selection Table for System Clock Divider ..........................................................................749

33-10

ATDMODE Field Descriptions ...........................................................................................750

33-11

ATDCAL Field Descriptions ...............................................................................................752

33-12

ATDPTS Field Descriptions ................................................................................................753

33-13

ATDINT Field Descriptions ................................................................................................754

33-14

ATDFLAG Field Descriptions ............................................................................................755

33-15

ATDCW Field Descriptions ................................................................................................756

33-16

Conversion Mode Selection Table.......................................................................................757

33-17

Numeric Examples for Result Values..................................................................................760

33-18

Channel Selection Table ......................................................................................................760

33-19

Conversion Start Behavior ...................................................................................................767

33-20

Conversion Continue Behavior............................................................................................767

33-21

Command Word #1 to Determine Gain and Offset .............................................................780

33-22

Bit Description of the Command Word ...............................................................................791

33-23

ATD Interrupt Vectors .........................................................................................................793

34-1

Port Pin and Peripheral Allocation ......................................................................................795

34-2

Expanded Mode Startup Pin Configuration .........................................................................796

34-3

PIM Peripheral Mode Configuration ...................................................................................798

34-4

PIM GPIO Mode Configuration ..........................................................................................799

34-5

PIM GPIO Input Mode Configuration .................................................................................799

34-6

Port Pin to Primary Peripheral Function Assignments ........................................................800

34-7

JTAG Pin Functions (Peripheral Mode) ..............................................................................803

34-8

PIM Bus Aborts ...................................................................................................................805

34-9

PIM Registers.......................................................................................................................806

34-10

Port Integration Module Memory Map Overview ...............................................................808

34-11

Port Integration Module Memory Map................................................................................809

34-12

CONFIGxx (Port A, B, C, D, F, G) Field Descriptions .......................................................817

34-13

CONFIGxx (Port A, B, C, D, F, G) Allowed Register Accesses.........................................818

34-14

CONFIGxx (Port E) Field Descriptions ...............................................................................819

34-15

CONFIGxx (Port E) Allowed Register Accesses.................................................................819

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