MAC7200 datasheet(81/976 Pages) FREESCALE

81 / 976 page

Features

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

— DMA transfers possible between system memories, SPIs, SCIs, I2C, ATD, eMIOS and General

Purpose I/Os

— Programmable DMA Channel Mux allows assignment of any DMA source to any of the 16

available DMA channels.

— All DMA transfers use dual address format.

— Programmable Transfer Control Descriptor stored in local DMA memory.

— Programmable Source and Destination address with configurable offset.

— Independent 32-bit Minor and 16-bit Major loop counters for “nested” transfers.

— Different final Source and Destination addresses allow circular Queue operation.

— Programmable priority levels for each channel.

— Bandwidth control for each channel.

— Programmable transfer sizes through Major and Minor loop counters.

— Independently Programmable read/write sizes.

— Periodic triggering of up to 8 channels.

— Round Robin channel prioritization

— Scatter-Gather functionality

— Inner Loop channel pre-emption

— Channel to Channel linking

— Software or Hardware start

•

Analog-to-Digital Converter

— Up to 16 analog input channels.

— 12-bit resolution 9-bit accuracy.

—2

μS minimum conversion time.

— Internal sample and hold circuitry.

— Pre-measurement discharge of internal Sample and Hold circuit possible for all channels.

— Programmable input sample time for various source impedances.

— Queued conversion sequences supported by DMA controller.

— Analog inputs configurable as external sample triggers.

— On-chip timer triggers for sampling.

•

Two 1M bit per second, CAN 2.0 A/B software compatible modules (FlexCAN)

— Full implementation of the CAN 2.0 protocol specification.

— Programmable bit rate up to 1Mbps.

— 32 flexible Mail Boxes of 0-8 bytes data length on all modules.

— All Mail Boxes configurable for either Rx/Tx.

— Unused Mail Boxes space can be used as general purpose RAM.

— Supports standard or extended messages.

— “Time Stamp”, based on a 16-bit free-running counter.

— Maskable interrupts.

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