MAC7200 datasheet(70/976 Pages) FREESCALE

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Terminology

MAC7200 Microcontroller Family Reference Manual, Rev. 2

lxx

Freescale Semiconductor

LSB

Least Significant Bit

LVR

Low Voltage Reset

MAC

Multiply and accumulate

MADD

Multiply-and-Add unit which is responsible for the raw result adjustment

MAS

Mid Address Space. 256KByte in size. If it exists, it may contain 4 x 64KByte subdivisions of

the H7Fb Array, or 2 x 128KByte subdivisions.

match

Match an event that occurs when the value of a match register becomes equal to the value of

the selected time-base.

Modulus Counter

MCU

Microcontroller Unit.

Message Buffer (MB) Internal FlexCAN data structure containing bytes received or to be transmitted to the CAN line,

as well as information about this data.

Memory Interface, contains all state machines and control logic needed for operation of the

H7Fb module.

MSB

Most Significant Bit

MUX

Multiplexer

NSM

New command word state machine

NVM

Non-Volatile Memory.

OpAmp

Operational Amplifier

OPWFM

Output Pulse Width and Frequency Modulation

OPWM

Output Pulse Width Modulation

OPWMC

Center Aligned Output Pulse Width Modulation

OSCCLK

Oscillator clock

Output Compare

The modification of an output signal due to a time base match.

Ownership Trace

Messaging (OTM)

Visibility of process/function that is currently executing.

PCS

Peripheral Chip Select

PEA

Pulse/Edge Accumulation

PEC

Pulse/Edge Counting

PFLASH

Platform Flash Controller

Pipeline

Act of initiating a bus cycle while another bus cycle is in progress. Thus the bus can have

multiple bus cycles pending at one time.

PIT

Periodic Interrupt Timer

PLL

Phase Locked Loop

POR

Power on Reset

Table ii. Terminology (Continued)

Terms

Description

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