MAC7200 datasheet(22/976 Pages) FREESCALE

22 / 976 page

MAC7200 Microcontroller Family Reference Manual, Rev. 2

xxii

Freescale Semiconductor

22.2.2.4

VDD33, VSS33 - Regulator Output1 (3.3V Logic) ................................................409

22.2.2.5

VDDPLL, VSSPLL - Regulator Output2 (3.3V PLL) ............................................409

22.2.2.6

VREGEN - Optional Regulator Enable ...................................................................409

22.3

Memory Map and Register Definition.............................................................................409

22.4

Functional Description.....................................................................................................409

22.4.1

General.........................................................................................................................409

22.4.2

REG - Regulator Core..................................................................................................409

22.4.2.1

Full Performance Mode ...........................................................................................410

22.4.3

POR - Power-On Reset ................................................................................................410

22.4.4

LVR15 - Low Voltage Reset ........................................................................................410

22.4.5

LVR33 - Low Voltage Reset ........................................................................................410

22.4.6

LVRPLL - Low Voltage Reset .....................................................................................410

22.4.7

Resets ...........................................................................................................................410

22.4.7.1

General.....................................................................................................................410

22.4.7.2

Description of Reset Operation ...............................................................................411

22.4.7.2.1

Power-On Reset (POR)........................................................................................411

22.4.7.2.2

Low Voltage Reset (LVR)....................................................................................411

22.5

Interrupts ..........................................................................................................................411

22.6

VREG Bus Aborts ...........................................................................................................411

22.7

VREG Differences from MAC71xx ................................................................................411

Chapter 23

Clock and Reset Generator (CRG)

23.1

Introduction......................................................................................................................413

23.1.1

CRG Overview ............................................................................................................413

23.1.2

CRG Block Diagram....................................................................................................413

23.1.3

Features........................................................................................................................414

23.1.4

Modes of Operation .....................................................................................................415

23.2

External Signal Description .............................................................................................415

23.2.1

Detailed Signal Descriptions .......................................................................................416

23.2.1.1

VDDPLL, VSSPLL ......................................................................................................416

23.2.1.2

XFC..........................................................................................................................416

23.2.1.3

RESET .....................................................................................................................416

23.2.1.4

CLKOUT/XCLKS ...................................................................................................416

23.3

Memory Map and Register Definition.............................................................................417

23.3.1

Memory Map ...............................................................................................................417

23.3.2

Register Descriptions...................................................................................................417

23.3.2.1

CRG Synthesizer Register (SYNR).........................................................................417

23.3.2.2

CRG Reference Divider Register (REFDV)............................................................418

23.3.2.3

CRG ARM Flag Register 1 (CTFLG) .....................................................................419

23.3.2.4

CRG Flags Register 2 (CRGFLG)...........................................................................420

23.3.2.5

CRG Interrupt Enable Register (CRGINT) .............................................................421

23.3.2.6

CRG Clock Select Register (CLKSEL)...................................................................421

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