MAC7200 datasheet(58/976 Pages) FREESCALE

58 / 976 page

MAC7200 Microcontroller Family Reference Manual, Rev. 2

lviii

Freescale Semiconductor

18-1

PFLASH Bus Aborts............................................................................................................361

18-2

Flash Terminology ...............................................................................................................362

18-3

Flash Block IPI User Registers ............................................................................................363

18-4

Flash PFCR1 Register Settings ............................................................................................365

18-5

Flash Controller APC and RWSC Settings..........................................................................366

18-6

MCM Block Flash Registers................................................................................................368

18-7

Flash Shadow Block Access Protection Types ....................................................................368

18-8

Flash Shadow Block Access Protection Address Ranges....................................................369

18-9

Flash Shadow Block Access Protection Types ....................................................................369

18-10

Flash Main Array Access Protection ...................................................................................370

18-11

Flash Program/Erase Blocks - MAC72x2............................................................................372

18-12

Flash Program/Erase Blocks - MAC72x1............................................................................373

18-13

System Censor Word Definition ..........................................................................................374

19-1

SRAM Address Mirroring ...................................................................................................378

19-2

Signal Width Variables ........................................................................................................381

19-3

Signal Properties ..................................................................................................................381

19-4

Signal Property Details ........................................................................................................383

19-5

pram_cs_b 64 Bit Behavior .................................................................................................384

19-6

Parity vs. Syndrome .............................................................................................................386

19-7

Unaligned Writes .................................................................................................................391

19-8

Late Write Hit Cases ............................................................................................................392

19-9

Parity Codes: ECC Bits vs. Data Bits ..................................................................................397

19-10

Hamming Parity Delay ........................................................................................................397

19-11

Modified Parity Codes: ECC Bits vs. Data Bits ..................................................................398

22-1

VREG_HIP7A - Signal Properties.......................................................................................408

22-2

VREG_HIP7A - Reset Sources ...........................................................................................410

23-1

Signal Properties ..................................................................................................................415

23-2

CRG Memory Map ..............................................................................................................417

23-3

CTFLG Field Descriptions ..................................................................................................419

23-4

CRGFLG Field Descriptions ...............................................................................................420

23-5

CRGINT Field Descriptions ................................................................................................421

23-6

CLKSEL Field Descriptions ................................................................................................422

23-7

PLLCTL Field Descriptions ................................................................................................423

23-8

SDMCTL Field Descriptions ...............................................................................................424

23-9

BDMCTL Field Descriptions ..............................................................................................424

23-10

MCU Configuration During Doze Mode .............................................................................431

23-11

Outcome of Clock Loss in Doze Mode................................................................................433

23-12

Entering CRG Modes...........................................................................................................435

23-13

Reset Summary ....................................................................................................................435

23-14

Reset Vector Selection .........................................................................................................436

23-15

CRG Interrupt Vectors .........................................................................................................440

23-16

CRG Bus Aborts ..................................................................................................................440

24-1

Clock Selection Based on XCLKS ......................................................................................446

24-2

Oscillator Modes ..................................................................................................................447

25-1

Module Memory Map ..........................................................................................................450

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