MAC7200 datasheet(45/976 Pages) FREESCALE

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MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

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17-4

Chip-Select Control Registers (CSCRn)..............................................................................347

17-5

Connections for External Memory Port Sizes .....................................................................350

17-6

Data Transfer State Transition Diagram ..............................................................................351

18-1

MAC72x1 Flash Blocks and Partitions................................................................................359

18-2

MAC72x2 Flash Blocks and Partitions................................................................................360

19-1

Simplified Platform Block Diagram ....................................................................................379

19-2

Block Diagram: PRAM_CTL ..............................................................................................380

19-3

Block Diagram: 39-bit ECC Decode ...................................................................................386

19-4

64-bit Read Followed by Two 32-bit Reads ........................................................................388

19-5

32/64-bit writes with reads...................................................................................................389

19-6

Back to Back 32/64-bit Writes.............................................................................................390

19-7

Less than 32-bit writes .........................................................................................................391

19-8

Late Write Hits.....................................................................................................................393

19-9

Multiple-Bit Error on AHB Read Request...........................................................................394

20-1

BAM Sequence ....................................................................................................................400

22-1

VREG_HIP7A Block Diagram............................................................................................407

23-1

Block diagram of CRG ........................................................................................................414

23-2

PLL Loop Filter Connections ..............................................................................................416

23-3

CRG Synthesizer Register (SYNR) .....................................................................................418

23-4

CRG Reference Divider Register (REFDV)........................................................................418

23-5

CRG Flag Register 1 (CTFLG)............................................................................................419

23-6

CRG Flag Register 2 (CRGFLG) ........................................................................................420

23-7

CRG Interrupt Enable Register (CRGINT) .........................................................................421

23-8

CRG Clock Select Register (CLKSEL) ...............................................................................422

23-9

CRG PLL Control Register (PLLCTL) ...............................................................................422

23-10

CRG DOZE Control Register (SDMCTL) ..........................................................................423

23-11

CRG BDM Control Register (BDMCTL) ...........................................................................424

23-12

PLL Functional Diagram .....................................................................................................425

23-13

System Clocks Generator.....................................................................................................427

23-14

System Clock and Peripheral Bus Clock Relationship ........................................................428

23-15

Check Window Example .....................................................................................................429

23-16

Sequence for Clock Quality Check......................................................................................429

23-17

Doze Mode Entry/Exit Sequence.........................................................................................432

23-18

RESET Timing.....................................................................................................................437

23-19

RESET Timing controlled by JTAG....................................................................................438

23-20

RESET Pin Tied to VDD (by a pull-up resistor) .................................................................439

23-21

RESET Pin Held Low Externally ........................................................................................439

24-1

OSC_ALC_HIP7A Block Diagram .....................................................................................444

24-2

ALC Oscillator Connections (XCLKS=1)...........................................................................445

24-3

External Clock Connections (XCLKS=0) ...........................................................................445

24-4

ALC Mode Clock Path.........................................................................................................448

24-5

External Clock Mode Clock Path ........................................................................................448

25-1

System Service Module Block Diagram..............................................................................449

25-2

Status (STATUS) Register...................................................................................................451

25-3

System Memory Configuration (MEMCONFIG) Register .................................................452

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