MAC7200 datasheet(124/976 Pages) FREESCALE

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Detailed Signal Descriptions

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

4.3.33

PC[8:15] / ADDR[8:15] / MDO[0:7] — Port C I/O Pins, External

Address Bus and Nexus Secondary

PC[8] to PC[15] are configurable general purpose input or output pins. The pins can be independently

configured to provide either high or reduced output drive, and also to enable or disable either a pull-up or

pull-down resistor on the pin. The pin is multiplexed with the external address bus lines Address 8 to

Address 15. Each pin can be independently configured to wake the system out of low-power mode (DOZE)

when an external signal is applied using the interrupt functionality. When the Nexus Secondary Port is

selected and active, these pin are used as Message Data Out outputs.

4.3.34

PD[0] / BWE[0] / MODB — Port D I/O Pin, External Bus Control &

Mode Selection

PD[0] is a configurable general purpose input or output pin. The pin can be configured to provide either

high or reduced output drive, and also to enable or disable either a pull-up or pull-down resistors on the

pin. The state of this pin is latched at the rising edge of RESET to determine the operating mode of the

MCU. After Reset the pin is able to be used as the General purpose input or output PD[0], or as a byte

select/byte write enable line for devices connected to the external bus. It can be configured to wake the

system out of low-power mode (DOZE) when an external signal is applied using the interrupt

functionality.

4.3.35

PD[1] / BWE[1] / MODA — Port D I/O Pin, External Bus Control &

Mode Selection

PD[1] is a configurable general purpose input or output pin. The pin can be configured to provide either

high or reduced output drive, and also to enable or disable either a pull-up or pull-down resistors on the

pin. The state of this pin is latched at the rising edge of RESET to determine the operating mode of the

MCU. After Reset the pin is able to be used as the General purpose input or output PD[1], or as a byte

select/byte write enable line for devices connected to the external bus. It can be configured to wake the

system out of low-power mode (DOZE) when an external signal is applied using the interrupt

functionality.

4.3.36

PD[2] / CLKOUT / XCLKS — Clock Out and Oscillator Selection

PD[2] is a configurable general purpose input pin (Note that general purpose output functionality is not

available). The pin can be configured to enable or disable either a pull-up or pull-down resistor on the pin.

The state of this pin is latched at the rising edge of RESET. Note that, unlike the rest of the hardware

configuration pins, the XCLKS pin is not latched during every system reset. It is only latched during a

Power On Reset or during a reset after a loss of clock has occurred. After Reset the pin is able to be used

as the General purpose input PD[2], or as a system clock for devices connected to the external bus. It can

be configured to wake the system out of low-power mode (DOZE) when an external signal is applied using

the interrupt functionality.

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