MAC7200 datasheet(34/976 Pages) FREESCALE

34 / 976 page

MAC7200 Microcontroller Family Reference Manual, Rev. 2

xxxiv

Freescale Semiconductor

32.11.1

Overview......................................................................................................................684

32.11.2

Detailed Signal Descriptions .......................................................................................684

32.11.2.1

EMIOSIn - eMIOS Unified Channel Input Signal ..................................................684

32.11.2.2

EMIOSOn - eMIOS Unified Channel Output Signal ..............................................684

32.12

Memory Map/Register Definition ...................................................................................684

32.12.1

Memory Map ...............................................................................................................684

32.12.2

Register Descriptions...................................................................................................685

32.12.2.1

eMIOS Module Configuration Register (MCR)......................................................685

32.12.2.2

eMIOS Global FLAG Register (GFLAG) ...............................................................687

32.12.2.3

eMIOS Output Update Disable (OUDIS)................................................................688

32.12.2.4

eMIOS Disable Channel (UCDIS) ..........................................................................689

32.12.2.5

eMIOS A Register (UCAn) .....................................................................................689

32.12.2.6

eMIOS B Register (UCBn)......................................................................................690

32.12.2.7

eMIOS Counter Register (UCCNTn) ......................................................................691

32.12.2.8

eMIOS Control Register (UCCRn) .........................................................................692

32.12.2.9

eMIOS Status Register (UCSRn) ............................................................................696

32.12.2.10

eMIOS Alternate A Register (ALTAn)....................................................................698

32.13

Functional Description.....................................................................................................699

32.13.1

Unified Channel (UC)..................................................................................................699

32.13.1.1

UC Modes of Operation...........................................................................................700

32.13.1.1.1

General purpose Input/Output mode (GPIO) Mode ............................................701

32.13.1.1.2

Single Action Input Capture (SAIC) Mode .........................................................701

32.13.1.1.3

Single Action Output Compare (SAOC) Mode...................................................701

32.13.1.1.4

Input Pulse Width Measurement (IPWM) Mode.................................................702

32.13.1.1.5

Input Period Measurement (IPM) Mode .............................................................704

32.13.1.1.6

Double Action Output Compare (DAOC) Mode ................................................705

32.13.1.1.7

Pulse/Edge Accumulation (PEA) Mode ..............................................................706

32.13.1.1.8

Pulse/Edge Counting (PEC) Mode ......................................................................708

32.13.1.1.9

Quadrature Decode (QDEC) Mode .....................................................................709

32.13.1.1.10

Windowed Programmable Time Accumulation (WPTA) Mode..........................711

32.13.1.1.11

Modulus Counter (MC) Mode .............................................................................711

32.13.1.1.12

Modulus Counter Buffered (MCB) Mode ...........................................................712

32.13.1.1.13

Pulse Width and Frequency Modulation (OPWFM) Mode.................................715

32.13.1.1.14

Pulse Width and Frequency Modulation Buffered (OPWFMB) Mode ...............716

32.13.1.1.15

Center Aligned Output Pulse Width Modulation with Dead-Time

(OPWMC) Mode .............................................................................................720

32.13.1.1.16

Center Aligned Output PWM Buffered with Dead-Time (OPWMCB) Mode ....723

32.13.1.1.17

Output Pulse Width Modulation (OPWM) Mode................................................727

32.13.1.1.18

Pulse Width Modulation Buffered (OPWMB) Mode..........................................729

32.13.1.2

Input Programmable Filter (IPF) .............................................................................732

32.13.1.3

Clock Prescaler (CP)................................................................................................733

32.13.1.4

Effect of Freeze on the Unified Channel .................................................................733

32.13.2

IP Bus Interface Unit (BIU).........................................................................................734

32.13.2.1

Effect of Freeze on the BIU.....................................................................................734

32.13.3

Global Clock Prescaler Submodule (GCP)..................................................................734

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