MAC7200 datasheet(35/976 Pages) FREESCALE

35 / 976 page

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

xxxv

32.13.3.1

Effect of Freeze on the GCP ....................................................................................734

32.14

Initialization/Application Information .............................................................................734

32.14.1

Considerations .............................................................................................................734

32.14.2

Application Information ..............................................................................................735

32.14.2.1

Time Base Generation .............................................................................................735

32.14.2.2

Coherent Accesses ...................................................................................................736

Chapter 33

A/D Converter (ATD)

33.1

Introduction to the ATD on MAC7200............................................................................737

33.2

ATD Features ...................................................................................................................737

33.3

ATD Implementation .......................................................................................................738

33.4

ATD External Pins ...........................................................................................................738

33.5

ATD Bus Aborts...............................................................................................................738

33.6

ATD Differences from MAC71xx ...................................................................................739

33.7

ATD Application Usage...................................................................................................740

33.7.1

Enabling the ATD ........................................................................................................740

33.7.2

Setting up the ATD ......................................................................................................740

33.7.3

Using external triggers.................................................................................................740

33.7.4

Using the system triggers.............................................................................................740

33.7.4.1

Example — Using System Triggers ........................................................................740

33.8

The DMADC1032 Module ..............................................................................................741

33.8.1

Overview......................................................................................................................741

33.8.2

Block Diagram.............................................................................................................742

33.8.3

Features of DMADC1032............................................................................................742

33.8.4

Modes of Operation .....................................................................................................743

33.9

Signal Description............................................................................................................743

33.9.1

Overview......................................................................................................................743

33.9.2

Signal Descriptions ......................................................................................................744

33.9.2.1

VDDA......................................................................................................................744

33.9.2.2

VSSA .......................................................................................................................744

33.9.2.3

VRH.........................................................................................................................745

33.9.2.4

VRL .........................................................................................................................745

33.9.2.5

REFBYPC................................................................................................................745

33.9.2.6

ANn..........................................................................................................................745

33.9.2.7

SYSTRIGn...............................................................................................................745

33.9.2.8

RX req / RX done ....................................................................................................745

33.9.2.9

TX reg / TX done.....................................................................................................745

33.9.2.10

SYSTRIG0/1, Interrupt, IP Bus Clock, System Clock ............................................745

33.10

Memory Map and Register Definition.............................................................................745

33.10.1

Module Memory Map..................................................................................................745

33.10.2

Register Descriptions...................................................................................................746

33.10.2.1

ATD Trigger Control Register (ATDTRIGCTL).....................................................746

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