MAC7200 datasheet(14/976 Pages) FREESCALE

14 / 976 page

MAC7200 Microcontroller Family Reference Manual, Rev. 2

xiv

Freescale Semiconductor

12.2.4.1.2

DMA Error Status (DMAES) ..............................................................................210

12.2.4.1.3

DMA Enable Request (DMAERQH, DMAERQL) ............................................212

12.2.4.1.4

DMA Enable Error Interrupt (DMAEEIH, DMAEEIL) .....................................214

12.2.4.1.5

DMA Set Enable Request (DMASERQ).............................................................215

12.2.4.1.6

DMA Clear Enable Request (DMACERQ).........................................................215

12.2.4.1.7

DMA Set Enable Error Interrupt (DMASEEI)....................................................216

12.2.4.1.8

DMA Clear Enable Error Interrupt (DMACEEI)................................................217

12.2.4.1.9

DMA Clear Interrupt Request (DMACINT) .......................................................217

12.2.4.1.10

DMA Clear Error (DMACERR) .........................................................................218

12.2.4.1.11

DMA Set START Bit (DMASSRT) ....................................................................218

12.2.4.1.12

DMA Clear DONE Status (DMACDNE)............................................................219

12.2.4.1.13

DMA Interrupt Request (DMAINTH, DMAINTL) ............................................220

12.2.4.1.14

DMA Error (DMAERRH, DMAERRL) .............................................................221

12.2.4.1.15

DMA Channel n Priority (DCHPRIn), n = 0,..., {15,31,63} ...............................222

12.2.4.1.16

Transfer Control Descriptor (TCD) .....................................................................223

12.2.5

DMA Performance.......................................................................................................232

12.2.6

Initialization/Application Information.........................................................................235

12.2.6.1

DMA Initialization...................................................................................................235

12.2.6.2

DMA Programming Errors ......................................................................................235

12.2.6.3

DMA Arbitration Mode Considerations ..................................................................235

12.2.6.3.1

Fixed Channel Arbitration ...................................................................................235

12.2.6.3.2

Round Robin Channel Arbitration.......................................................................236

12.2.6.4

DMA Transfer..........................................................................................................236

12.2.6.4.1

Single request ......................................................................................................236

12.2.6.4.2

Multiple requests .................................................................................................237

12.2.6.5

TCD Status...............................................................................................................238

12.2.6.5.1

Minor loop complete ...........................................................................................238

12.2.6.5.2

Active channel TCD reads...................................................................................239

12.2.6.5.3

Preemption status.................................................................................................239

12.2.6.6

Channel Linking ......................................................................................................240

12.2.6.7

Dynamic Programming............................................................................................240

12.2.6.7.1

Dynamic priority changing ..................................................................................240

12.2.6.7.2

Dynamic channel linking and dynamic scatter/gather.........................................241

12.2.6.8

Hardware Request Release Timing..........................................................................242

Chapter 13

Miscellaneous Control Module (MCM)

13.1

Introduction......................................................................................................................243

13.1.1

Overview......................................................................................................................243

13.1.2

Features........................................................................................................................243

13.2

Memory Map/Register Definition ...................................................................................243

13.2.1

Memory Map ...............................................................................................................244

13.2.2

Register Descriptions...................................................................................................245

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