MAC7200 datasheet(60/976 Pages) FREESCALE

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MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

28-13

IMASK1 Field Descriptions ................................................................................................526

28-14

IFLAG1 Field Descriptions .................................................................................................527

28-15

RXIMRn Field Descriptions ................................................................................................528

28-16

Time Segment Syntax ..........................................................................................................536

28-17

CAN Standard Compliant Bit Time Segment Settings........................................................536

28-18

Minimum Ratio Between Peripheral Clock Frequency and CAN Bit Rate.........................537

28-19

Wake-up from Doze Mode ..................................................................................................539

28-20

Wake-up from Stop Mode ...................................................................................................540

29-1

Module Memory Map ..........................................................................................................549

29-2

IBAD Field Descriptions .....................................................................................................550

29-3

IBFD Field Descriptions ......................................................................................................551

29-4

I-Bus Multiplier Factor ........................................................................................................551

29-5

I-Bus Prescaler Divider Values............................................................................................551

29-6

I-Bus Tap and Prescale Values ............................................................................................551

29-7

I2C Divider and Hold Values ...............................................................................................554

29-8

IBCR Field Descriptions......................................................................................................557

29-9

IBSR Field Descriptions ......................................................................................................558

29-10

IBIC Field Descriptions .......................................................................................................560

29-11

Interrupt Summary ...............................................................................................................564

30-1

CPOL and CPHA Control Bits ............................................................................................576

30-2

DSPI External Pins ..............................................................................................................577

30-3

DSPI Bus Aborts..................................................................................................................577

30-4

DSPI Maximum Baud Rate Parameters...............................................................................578

30-5

DSPI SCK Duty Cycle Calculation .....................................................................................578

30-6

Signal Properties ..................................................................................................................581

30-7

DSPI Memory Map..............................................................................................................583

30-8

DSPI_MCR Field Descriptions............................................................................................584

30-9

DSPI_TCR Field Descriptions.............................................................................................587

30-10

DSPI_CTARn Field Descriptions........................................................................................588

30-11

DSPI SCK Duty Cycle.........................................................................................................590

30-12

DSPI Transfer Frame Size ..................................................................................................591

30-13

DSPI PCS to SCK Delay Scaler .........................................................................................591

30-14

DSPI After SCK Delay Scaler ............................................................................................591

30-15

DSPI Delay after Transfer Scaler ......................................................................................592

30-16

DSPI Baud Rate Scaler .......................................................................................................592

30-17

DSPI_SR Field Descriptions................................................................................................593

30-18

DSPI_RSER Field Descriptions ..........................................................................................595

30-19

DSPI_PUSHR Field Descriptions........................................................................................597

30-20

DSPI_POPR Field Descriptions ..........................................................................................598

30-21

DSPI_TXFRn Field Descriptions ........................................................................................599

30-22

DSPI_RXFRn Field Descriptions ........................................................................................599

30-23

State Transitions for Start and Stop of DSPI Transfers .......................................................602

30-24

Baud Rate Computation Example........................................................................................606

30-25

PCS to SCK Delay Computation Example ..........................................................................606

30-26

After SCK Delay Computation Example.............................................................................606

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