MAC7200 datasheet(17/976 Pages) FREESCALE

17 / 976 page

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

xvii

14.8.1.11

FIQ Interrupt Acknowledge Register (FIQIACK) ..................................................305

14.9

Functional Description.....................................................................................................306

14.9.1

Interrupt Controller Theory of Operation ....................................................................306

14.9.1.1

Interrupt Recognition...............................................................................................307

14.9.1.2

Interrupt Prioritization and Level Masking .............................................................307

14.9.1.3

Vector Generation during IACK..............................................................................307

14.9.1.4

Multiple Controller Requirements ...........................................................................308

14.9.2

Performance .................................................................................................................309

14.10

Initialization/Application Information .............................................................................310

14.10.1

Initialization .................................................................................................................310

14.10.2

Typical Applications ....................................................................................................310

14.10.3

Interrupt Service Routines ...........................................................................................311

Chapter 15

MAC7200 Crossbar Switch (AXBS)

15.1

Introduction......................................................................................................................313

15.1.1

Overview......................................................................................................................314

15.1.2

Features........................................................................................................................314

15.1.3

AXBS Integration ........................................................................................................314

15.1.4

Modes of Operation .....................................................................................................315

15.2

External Signal Description .............................................................................................315

15.3

Memory Map Definition ..................................................................................................315

15.4

Register Descriptions .......................................................................................................316

15.4.1

Priority Register..........................................................................................................316

15.4.2

Control Register...........................................................................................................317

15.5

Functional Description.....................................................................................................319

15.5.1

Arbitration....................................................................................................................319

15.5.1.1

Fixed Priority Operation ..........................................................................................319

15.5.1.2

Round-Robin Priority Operation .............................................................................320

15.5.2

Priority Assignment .....................................................................................................320

15.6

Initialization/Application Information .............................................................................320

15.7

AXBS Bus Aborts............................................................................................................320

15.7.1

IPI Register Interface ...................................................................................................320

15.7.2

Master/Slave Interface .................................................................................................322

15.8

AXBS Differences from MAC71xx ................................................................................322

Chapter 16

AHB to IPI Bridge (AIPS)

16.1

Introduction......................................................................................................................323

16.1.1

Features........................................................................................................................323

16.1.2

General Operation........................................................................................................324

16.2

AIPS Protocol ..................................................................................................................325

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