ATtiny43U datasheet(137/182 Pages) ATMEL

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137

8048B–AVR–03/09

18.7

Preventing Flash Corruption

During periods of low V

CC, the Flash program can be corrupted because the supply voltage is

too low for the CPU and the Flash to operate properly. These issues are the same as for board

level systems using the Flash, and the same design solutions should be applied.

A Flash program corruption can be caused by two situations when the voltage is too low. First, a

regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly,

the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions

is too low.

Flash corruption can easily be avoided by following these design recommendations (one is

sufficient):

Keep the AVR RESET active (low) during periods of insufficient power supply voltage.

This can be done by enabling the internal Brown-out Detector (BOD) if the operating

voltage matches the detection level. If not, an external low V

CC reset protection circuit

can be used. If a reset occurs while a write operation is in progress, the write operation

will be completed provided that the power supply voltage is sufficient.

Keep the AVR core in Power-down sleep mode during periods of low V

CC. This will pre-

vent the CPU from attempting to decode and execute instructions, effectively protecting

the SPMCSR Register and thus the Flash from unintentional writes.

18.8

Programming Time for Flash when Using SPM

The calibrated RC Oscillator is used to time Flash accesses. Table 18-1 shows the typical pro-

gramming time for Flash accesses from the CPU.

18.9

18.9.1

SPMCSR – Store Program Memory Control and Status Register

The Store Program Memory Control and Status Register contains the control bits needed to con-

trol the Program memory operations.

• Bits 7:5 – Res: Reserved Bits

These bits are reserved and will always read zero.

• Bit 4 – CTPB: Clear Temporary Page Buffer

If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be

cleared and the data will be lost.

Table 18-1.

SPM Programming Time

Symbol

Min Programming Time

Max Programming Time

Flash write (Page Erase, Page Write, and

write Lock bits by SPM)

3.7 ms

4.5 ms

Bit

210

0x37 (0x57)

–

CTPB

RFLB

PGWRT

PGERS

SPMEN

SPMCSR

Read/Write

R/W

Initial Value

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