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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ATtiny43U датащи(PDF) 16 Page - ATMEL Corporation |
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ATtiny43U датащи(HTML) 16 Page - ATMEL Corporation |
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16 / 182 page  16 8048B–AVR–03/09 ATtiny43U The direct addressing reaches the entire data space. The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y- or Z-register. When using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and the 256 bytes of internal data SRAM in ATtiny43U are all accessible through all these addressing modes. The Register File is described in “General Purpose Register File” on page 10. Figure 5-2. Data Memory Map 5.3.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk CPU cycles as described in Figure 5-3 on page 16. Figure 5-3. On-chip Data SRAM Access Cycles 5.4 EEPROM Data Memory The ATtiny43U contains 64 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and 32 Registers 64 I/O Registers Internal SRAM (256 x 8) 0x0000 - 0x001F 0x0020 - 0x005F 0x15F 0x0060 Data Memory clk WR RD Data Data Address Address valid T1 T2 T3 Compute Address CPU Memory Access Instruction Next Instruction |
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