ATtiny43U datasheet(99/182 Pages) ATMEL

99 / 182 page

8048B–AVR–03/09

tem clock frequency (f

ExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses

sampling, the maximum frequency of an external clock it can detect is half the sampling fre-

quency (Nyquist sampling theorem). However, due to variation of the system clock frequency

and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is

recommended that maximum frequency of an external clock source is less than f

clk_I/O/2.5.

An external clock source can not be prescaled.

Figure 13-2. Prescaler for Timer/Countern

Note:

1. The synchronization logic on the input pins (

Tn) is shown in Figure 13-1 on page 98.

13.3

13.3.1

GTCCR – General Timer/Counter Control Register

• Bit 7 – TSM: Timer/Counter Synchronization Mode

Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the

value that is written to the PSR10 bit is kept, hence keeping the Prescaler Reset signal asserted.

This ensures that the Timer/Counter is halted and can be configured without the risk of advanc-

ing during configuration. When the TSM bit is written to zero, the PSR10 bit is cleared by

hardware, and the Timer/Counter start counting.

• Bit 0 – PSR10: Prescaler Reset Timer/Counter

When this bit is one, the Timer/Counter prescaler will be reset. This bit is normally cleared imme-

diately by hardware, except if the TSM bit is set.

PSR10

Clear

clk

I/O

Synchronization

CSn0

CSn1

CSn2

TIMER/COUNTERn CLOCK SOURCE

Bit

0x23 (0x43)

TSM

–

PSR10

GTCCR

Read/Write

R/W

Initial Value

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