ATtiny43U datasheet(80/182 Pages) ATMEL

80 / 182 page

8048B–AVR–03/09

ATtiny43U

12.2.1

Registers

The Timer/Counter (TCNTn) and Output Compare Registers (OCRnA and OCRnB) are 8-bit

registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the

Timer Interrupt Flag Register (TIFRn). All interrupts are individually masked with the Timer Inter-

rupt Mask Register (TIMSKn). TIFRn and TIMSKn are not shown in the figure.

The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on

the Tn pin. The Clock Select logic block controls which clock source and edge the Timer/Counter

uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source

is selected. The output from the Clock Select logic is referred to as the timer clock (clk

Tn).

The double buffered Output Compare Registers (OCRnA and OCRnB) is compared with the

Timer/Counter value at all times. The result of the compare can be used by the Waveform Gen-

erator to generate a PWM or variable frequency output on the Output Compare pins (OCnA and

OCnB). See “Output Compare Unit” on page 81 for details. The Compare Match event will also

set the Compare Flag (OCFnA or OCFnB) which can be used to generate an Output Compare

interrupt request.

12.2.2

Definitions

The definitions in Table 12-1 are used extensively throughout the document.

12.3

Timer/Counter Clock Sources

The Timer/Counter can be clocked by an internal or an external clock source. The clock source

is selected by the Clock Select logic which is controlled by the Clock Select (CSn2:0) bits

located in the Timer/Counter Control Register (TCCRnB). For details on clock sources and pres-

caler, see “Timer/Counter Prescaler” on page 98.

12.4

Counter Unit

The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure

12-2 on page 81 shows a block diagram of the counter and its surroundings.

Table 12-1.

Definitions

BOTTOM

The counter reaches the BOTTOM when it becomes 0x00.

MAX

The counter reaches its MAXimum when it becomes 0xFF (decimal 255).

TOP

The counter reaches the TOP when it becomes equal to the highest value in the

count sequence. The TOP value can be assigned to be the fixed value 0xFF

(MAX) or the value stored in the OCRnA Register. The assignment is depen-

dent on the mode of operation.

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