ATtiny43U datasheet(81/182 Pages) ATMEL

81 / 182 page

8048B–AVR–03/09

Figure 12-2. Counter Unit Block Diagram

Signal description (internal signals):

count

Increment or decrement TCNTn by 1.

direction

Select between increment and decrement.

clear

Clear TCNTn (set all bits to zero).

clk

Timer/Counter clock, referred to as clk

Tn in the following.

top

Signalize that TCNTn has reached maximum value.

bottom

Signalize that TCNTn has reached minimum value (zero).

Depending of the mode of operation used, the counter is cleared, incremented, or decremented

at each timer clock (clk

Tn). clkTn can be generated from an external or internal clock source,

selected by the Clock Select bits (CSn2:0). When no clock source is selected (CSn2:0 = 0) the

timer is stopped. However, the TCNTn value can be accessed by the CPU, regardless of

whether clk

Tn is present or not. A CPU write overrides (has priority over) all counter clear or

count operations.

The counting sequence is determined by the setting of the WGMn1 and WGMn0 bits located in

the Timer/Counter Control Register (TCCRnA) and the WGMn2 bit located in the Timer/Counter

Control Register B (TCCRnB). There are close connections between how the counter behaves

(counts) and how waveforms are generated on the Output Compare output OCnA. For more

details about advanced counting sequences and waveform generation, see “Modes of Opera-

tion” on page 84.

The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation selected by

the WGMn1:0 bits. TOVn can be used for generating a CPU interrupt.

12.5

Output Compare Unit

The 8-bit comparator continuously compares TCNTn with the Output Compare Registers

(OCRnA and OCRnB). Whenever TCNTn equals OCRnA or OCRnB, the comparator signals a

match. A match will set the Output Compare Flag (OCFnA or OCFnB) at the next timer clock

cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output

Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is exe-

cuted. Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit

location. The Waveform Generator uses the match signal to generate an output according to

operating mode set by the WGMn2:0 bits and Compare Output mode (COMnx1:0) bits. The max

and bottom signals are used by the Waveform Generator for handling the special cases of the

extreme values in some modes of operation. See “Modes of Operation” on page 84.

Figure 12-3 on page 82 shows a block diagram of the Output Compare unit.

DATA BUS

TCNTn

Control Logic

count

TOVn

(Int.Req.)

Clock Select

top

Edge

Detector

( From Prescaler )

clk

bottom

direction

clear

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