ATtiny43U datasheet(96/182 Pages) ATMEL

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8048B–AVR–03/09

ATtiny43U

12.9.12

TIMSK1 – Timer/Counter 1 Interrupt Mask Register

• Bits 7:3 – Res: Reserved Bits

These bits are reserved and will always read zero.

• Bit 2 – OCIEnB: Timer/Countern Output Compare Match B Interrupt Enable

When the OCIEnB bit is written to one, and the I-bit in the Status Register is set, the

Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if

a Compare Match in Timer/Countern occurs, i.e., when the OCFnB bit is set in the Timer/Coun-

ter Interrupt Flag Register – TIFRn.

• Bit 1 – OCIEnA: Timer/Countern Output Compare Match A Interrupt Enable

When the OCIEnA bit is written to one, and the I-bit in the Status Register is set, the

Timer/Countern Compare Match A interrupt is enabled. The corresponding interrupt is executed

if a Compare Match in Timer/Countern occurs, i.e., when the OCFnA bit is set in the

Timer/Counter n Interrupt Flag Register – TIFRn.

• Bit 0 – TOIEn: Timer/Countern Overflow Interrupt Enable

When the TOIEn bit is written to one, and the I-bit in the Status Register is set, the Timer/Coun-

tern Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in

Timer/Countern occurs, i.e., when the TOVn bit is set in the Timer/Counter n Interrupt Flag Reg-

ister – TIFRn.

12.9.13

TIFR0 – Timer/Counter 0 Interrupt Flag Register

12.9.14

TIFR1 – Timer/Counter 1 Interrupt Flag Register

• Bits 7:3 – Res: Reserved Bits

These bits are reserved and will always read zero.

• Bit 2 – OCFnB: Output Compare Flag n B

The OCFnB bit is set when a Compare Match occurs between the Timer/Countern and the data

in OCRnB – Output Compare Registern B. OCFnB is cleared by hardware when executing the

corresponding interrupt handling vector. Alternatively, OCFnB is cleared by writing a logic one to

the flag. When the I-bit in SREG, OCIEnB (Timer/Counter Compare B Match Interrupt Enable),

and OCFnB are set, the Timer/Countern Compare Match Interrupt is executed.

Bit

7654

0x0C (0x2C)

––––

–

OCIE1B

OCIE1A

TOIE1

TIMSK1

Read/Write

RRRR

R/W

Initial Value

0000

Bit

765

432

0x38 (0x58)

–

OCF0B

OCF0A

TOV0

TIFR0

Read/Write

RRR

R/W

Initial Value

Bit

765

432

0x0B (0x2B)

–

OCF1B

OCF1A

TOV1

TIFR1

Read/Write

RRR

R/W

Initial Value

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