ATtiny43U datasheet(27/182 Pages) ATMEL

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8048B–AVR–03/09

6.2.5

Clock Startup Sequence

Any clock source needs a sufficient V

CC to start oscillating and a minimum number of oscillating

cycles before it can be considered stable.

To ensure sufficient V

CC, the device issues an internal reset with a time-out delay (tTOUT) after

the device reset is released by all other reset sources. The section “System Control and Reset”

on page 48 describes the start conditions for the internal reset. The delay (t

TOUT) is timed from

the Watchdog Oscillator and the number of cycles in the delay is set by the SUTn and CKSELn

fuse bits. The available delays are shown in Table 6-8.

Note:

The frequency of the Watchdog Oscillator is voltage dependent as shown in TBD.

The main purpose of the delay is to keep the AVR in reset until V

CC has risen to a sufficient level.

The delay will not monitor the actual voltage and, hence, the user must make sure the delay time

is longer than the V

CC rise time. If this is not possible, an internal or external Brown-Out Detec-

tion circuit should be used. A BOD circuit ensures there is sufficient V

CC before it releases the

reset line, and the time-out delay can then be disabled. It is not recommended to disable the

time-out delay without implementing a Brown-Out Detection circuit.

The oscillator is required to oscillate for a minimum number of cycles before the clock is consid-

ered stable. An internal ripple counter monitors the oscillator output clock, and keeps the internal

reset active for a given number of clock cycles. The reset is then released and the device will

start to execute.

The start-up sequence for the clock includes both the time-out delay and the start-up time when

the device starts up from reset. When starting up from Power-down mode, V

CC is assumed to be

at a sufficient level and only the start-up time is included.

6.3

System Clock Prescaler

The ATtiny43U has a system clock prescaler, which means the system clock can be divided as

described in section “CLKPR – Clock Prescale Register” on page 28. This feature can be used

to lower system clock frequency and decrease the power consumption at times when require-

ments for processing power is low. This can be used with all clock source options, and it will

affect the clock frequency of the CPU and all synchronous peripherals. Clock signals clk

I/O,

clk

ADC, clkCPU, and clkFLASH are divided by a factor as shown in Table 20-4 on page 158.

6.3.1

Switching Time

When changing prescaler settings, the System Clock Prescaler ensures that no glitches occurs

in the clock system. It also ensures that no intermediate frequency is higher than either the clock

frequency corresponding to the previous setting or the clock frequency corresponding to the new

setting. The ripple counter of the prescaler runs at the same frequency as the undivided clock,

which may be higher than the CPU's clock frequency. Hence, even if it was readable, it is not

possible to determine the state of the prescaler, and it is not possible to predict the exact time it

takes to switch from one clock division to the other. From the time the CLKPS values are written,

Table 6-8.

Number of Watchdog Oscillator Cycles

Typ Time-out (VCC = 5.0V)

Typ Time-out (VCC = 3.0V)

Number of Cycles

0 ms

4.1 ms

4.3 ms

512

65 ms

69 ms

8K (8,192)

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