ATtiny43U datasheet(52/182 Pages) ATMEL

52 / 182 page

8048B–AVR–03/09

ATtiny43U

clock cycle periods can be selected to determine the reset period. If the reset period expires

without another Watchdog Reset, the ATtiny43U resets and executes from the Reset Vector.

For timing details on the Watchdog Reset, refer to Table 9-3 on page 56.

The Wathdog Timer can also be configured to generate an interrupt instead of a reset. This can

be very helpful when using the Watchdog to wake-up from Power-down.

To prevent unintentional disabling of the Watchdog or unintentional change of time-out period,

two different safety levels are selected by the fuse WDTON as shown in Table 9-1. See “Timed

Sequences for Changing the Configuration of the Watchdog Timer” on page 52 for details.

Figure 9-7.

Watchdog Timer

9.8.1

Timed Sequences for Changing the Configuration of the Watchdog Timer

The sequence for changing configuration differs slightly between the two safety levels. Separate

procedures are described for each level.

9.8.1.1

Safety Level 1

In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit

to one without any restriction. A timed sequence is needed when disabling an enabled Watch-

dog Timer. To disable an enabled Watchdog Timer, the following procedure must be followed:

In the same operation, write a logic one to WDCE and WDE. A logic one must be writ-

ten to WDE regardless of the previous value of the WDE bit.

Within the next four clock cycles, in the same operation, write the WDE and WDP bits

as desired, but with the WDCE bit cleared.

Table 9-1.

WDT Configuration as a Function of the Fuse Settings of WDTON

WDTON

Safety

Level

WDT Initial

State

How to Disable the

WDT

How to Change Time-

out

Unprogrammed

Disabled

Timed sequence

No limitations

Programmed

Enabled

Always enabled

Timed sequence

MCU RESET

WATCHDOG

PRESCALER

128 kHz

OSCILLATOR

WATCHDOG

RESET

WDP0

WDP1

WDP2

WDP3

WDE

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