ATtiny43U datasheet(61/182 Pages) ATMEL

61 / 182 page

8048B–AVR–03/09

• Bit 6 – INTF0: External Interrupt Flag 0

When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set

(one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the cor-

responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.

Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared

when INT0 is configured as a level interrupt.

• Bit 5 – PCIF1: Pin Change Interrupt Flag 1

When a logic change on any PCINT15..8 pin triggers an interrupt request, PCIF1 becomes set

(one). If the I-bit in SREG and the PCIE1 bit in GIMSK are set (one), the MCU will jump to the

corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-

natively, the flag can be cleared by writing a logical one to it.

• Bit 4 – PCIF0: Pin Change Interrupt Flag 0

When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set

(one). If the I-bit in SREG and the PCIE0 bit in GIMSK are set (one), the MCU will jump to the

corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-

natively, the flag can be cleared by writing a logical one to it.

10.3.4

PCMSK1 – Pin Change Mask Register 1

• Bits 7:0 – PCINT[15:8]: Pin Change Enable Mask 15:8

Each PCINT15:8 bit selects whether pin change interrupt is enabled on the corresponding I/O

pin, or not. If PCINT15:8 is set and the PCIE1 bit in GIMSK is set, pin change interrupt is

enabled on the corresponding I/O pin. If PCINT15:8 is cleared, pin change interrupt on the corre-

sponding I/O pin is disabled.

10.3.5

PCMSK0 – Pin Change Mask Register 0

• Bits 7:0 – PCINT[7:0]: Pin Change Enable Mask 7:0

Each PCINT7:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin.

If PCINT7:0 is set and the PCIE0 bit in GIMSK is set, pin change interrupt is enabled on the cor-

responding I/O pin. If PCINT7:0 is cleared, pin change interrupt on the corresponding I/O pin is

disabled.

Bit

76543210

0x20 (0x40)

PCINT15

PCINT14

PCINT13

PCINT12

PCINT11

PCINT10

PCINT9

PCINT8

PCMSK1

Read/Write

R/W

Initial Value

00000000

Bit

765

432

0x12 (0x32)

PCINT7

PCINT6

PCINT5

PCINT4

PCINT3

PCINT2

PCINT1

PCINT0

PCMSK0

Read/Write

R/W

Initial Value

ATtiny43U датащи(PDF) 61 Page - ATMEL Corporation

ATtiny43U датащи(HTML) 61 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL