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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ATtiny43U датащи(PDF) 65 Page - ATMEL Corporation |
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ATtiny43U датащи(HTML) 65 Page - ATMEL Corporation |
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65 / 182 page  65 8048B–AVR–03/09 Figure 11-3. Synchronization when Reading an Externally Applied Pin value Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indi- cated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed between ½ and 1½ system clock period depending upon the time of assertion. When reading back a software assigned pin value, a nop instruction must be inserted as indi- cated in Figure 11-4 on page 65. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay tpd through the synchronizer is one system clock period. Figure 11-4. Synchronization when Reading a Software Assigned Pin Value XXX in r17, PINx 0x00 0xFF INSTRUCTIONS SYNC LATCH PINxn r17 XXX SYSTEM CLK t pd, max t pd, min out PORTx, r16 nop in r17, PINx 0xFF 0x00 0xFF SYSTEM CLK r16 INSTRUCTIONS SYNC LATCH PINxn r17 t pd |
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