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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ATtiny43U датащи(PDF) 24 Page - ATMEL Corporation |
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ATtiny43U датащи(HTML) 24 Page - ATMEL Corporation |
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24 / 182 page  24 8048B–AVR–03/09 ATtiny43U 6.1.4 ADC Clock – clk ADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results. 6.2 Clock Sources The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules. Note: 1. For all fuses “1” means unprogrammed while “0” means programmed. 6.2.1 External Clock To drive the device from an external clock source, CLKI should be driven as shown in Figure 6-2 on page 24. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000” (see Table 6-2). Figure 6-2. External Clock Drive Configuration Table 6-1. Device Clocking Options Select(1) Device Clocking Option CKSEL3..0 External Clock (see page 24) 0000 Calibrated Internal 8 MHz Oscillator (see page 25) 0010 Internal 128 kHz Oscillator (see page 26) 0011 Reserved 0001, 0100-1111 Table 6-2. Crystal Oscillator Clock Frequency CKSEL3..0 Frequency 0000 0 - 8 MHz EXTERNAL CLOCK SIGNAL CLKI GND |
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