ATtiny43U datasheet(28/182 Pages) ATMEL

28 / 182 page

8048B–AVR–03/09

ATtiny43U

it takes between T1 + T2 and T1 + 2 * T2 before the new clock frequency is active. In this inter-

val, two active clock edges are produced. Here, T1 is the previous clock period, and T2 is the

period corresponding to the new prescaler setting.

6.4

Clock Output Buffer

The device can output the system clock on the CLKO pin. To enable the output, the CKOUT

Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other cir-

cuits on the system. The clock also will be output during reset, and the normal operation of I/O

pin will be overridden when the fuse is programmed. Any clock source, including the internal RC

Oscillator, can be selected when the clock is output on CLKO. If the System Clock Prescaler is

used, it is the divided system clock that is output.

6.5

6.5.1

OSCCAL – Oscillator Calibration Register

• Bits 7:0 – CAL[7:0]: Oscillator Calibration Value

The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to

remove process variations from the oscillator frequency. A pre-programmed calibration value is

automatically written to this register during chip reset, giving the Factory calibrated frequency as

specified in Table 20-2 on page 157. The application software can write this register to change

the oscillator frequency. The oscillator can be calibrated to frequencies as specified in Table 20-

2 on page 157. Calibration outside that range is not guaranteed.

Note that this oscillator is used to time EEPROM and Flash write accesses, and these write

times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more

than 8.8 MHz. Otherwise, the EEPROM or Flash write may fail.

The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the

lowest frequency range, setting this bit to 1 gives the highest frequency range. The two fre-

quency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a higher

frequency than OSCCAL = 0x80.

The CAL6..0 bits are used to tune the frequency within the selected range. A setting of 0x00

gives the lowest frequency in that range, and a setting of 0x7F gives the highest frequency in the

range.

6.5.2

CLKPR – Clock Prescale Register

• Bit 7 – CLKPCE: Clock Prescaler Change Enable

The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE

bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is

Bit

654

CAL7

CAL6

CAL5

CAL4

CAL3

CAL2

CAL1

CAL0

OSCCAL

Read/Write

R/W

Initial Value

Device Specific Calibration Value

Bit

3210

CLKPCE

–

CLKPS3

CLKPS2

CLKPS1

CLKPS0

CLKPR

Read/Write

R/W

Initial Value

See Bit Description

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