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ATtiny43U датащи(PDF) 93 Page - ATMEL Corporation |
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ATtiny43U датащи(HTML) 93 Page - ATMEL Corporation |
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93 / 182 page ![]() 93 8048B–AVR–03/09 Note: 1. MAX = 0xFF, BOTTOM = 0x00 12.9.3 TCCR0B – Timer/Counter Control Register B 12.9.4 TCCR1B – Timer/Counter Control Register B • Bit 7 – FOCnA: Force Output Compare A The FOCnA bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCRnB is written when operating in PWM mode. When writing a logical one to the FOCnA bit, an immediate Compare Match is forced on the Waveform Generation unit. The OCnA output is changed according to its COMnA1:0 bits setting. Note that the FOCnA bit is implemented as a strobe. Therefore it is the value present in the COMnA1:0 bits that determines the effect of the forced compare. A FOCnA strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCRnA as TOP. The FOCnA bit is always read as zero. • Bit 6 – FOCnB: Force Output Compare B The FOCnB bit is only active when the WGM bits specify a non-PWM mode. Table 12-8. Waveform Generation Mode Bit Description Mode WGMn2 WGMn1 WGMn0 Timer/Counter Mode of Operation TOP Update of OCRx at TOV Flag Set on (1) 0 0 0 0 Normal 0xFF Immediate MAX 1 001 PWM, Phase Correct 0xFF TOP BOTTOM 2 0 1 0 CTC OCRnA Immediate MAX 3 0 1 1 Fast PWM 0xFF TOP MAX 4 100 Reserved – – – 5 101 PWM, Phase Correct OCRnA TOP BOTTOM 6 110 Reserved – – – 7 111 Fast PWM OCRnA TOP TOP Bit 7 6 5 4 3 2 1 0 0x33 (0x53) FOC0A FOC0B – – WGM02 CS02 CS01 CS00 TCCR0B Read/Write W W R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 0x2E (0x4E) FOC1A FOC1B – – WGM12 CS12 CS11 CS10 TCCR1B Read/Write W W R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 |
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