| поискавой системы для электроныых деталей |
|
ATtiny43U датащи(PDF) 58 Page - ATMEL Corporation |
|
|
|||||||||||||||||||||||||||||
ATtiny43U датащи(HTML) 58 Page - ATMEL Corporation |
|
58 / 182 page ![]() 58 8048B–AVR–03/09 ATtiny43U 0x0008 rjmp TIM0_COMPA ; Timer0 Compare A Handler 0x0009 rjmp TIM0_COMPB ; Timer0 Compare B Handler 0x000A rjmp TIM0_OVF ; Timer0 Overflow Handler 0x000B rjmp ANA_COMP ; Analog Comparator Handler 0x000C rjmp ADC ; ADC Conversion Handler 0x000D rjmp EE_RDY ; EEPROM Ready Handler 0x000E rjmp USI_STR ; USI Start Handler 0x000F rjmp USI_OVF ; USI Overflow Handler ; 0x0010 RESET: ldi r16, low(RAMEND); Main program start 0x0011 out SPL,r16 ; Set Stack Pointer to top of RAM 0x0012 sei ; Enable interrupts 0x0013 <instr> xxx ... ... ... ... 10.2 External Interrupts The External Interrupts are triggered by the INT0 pin or any of the PCINT pins. Observe that, if enabled, the interrupts will trigger even if INT0 or the PCINT pins are configured as outputs. This feature provides a way of generating a software interrupt, as follows. • Pin Change Interrupt PCI0 triggers if a pin in PCINT7:0 is toggled while enabled • Pin Change Interrupt PCI1 triggers if a pin in PCINT15:8 is toggled while enabled The PCMSK0 and PCMSK1 Registers control which pins contribute to the pin change interrupts. Pin change interrupts on PCINT15..0 are detected asynchronously. This means that these inter- rupts can be used for waking the part also from sleep modes other than Idle mode. The INT0 interrupt can be triggered by a falling or rising edge, or a low level. This is configured as described in “MCUCR – MCU Control Register” on page 59. When the INT0 interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Low level and edge interrupts on INT0 are detected asynchronously. This implies that these interrupts can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode. Note that if a level triggered interrupt is used for wake-up from Power-down, the required level must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of the Start-up Time, the MCU will still wake up, but no interrupt will be generated and execution will continue from the instruction following the SLEEP command. The start-up time is defined by the SUT and CKSEL fuses, as described in “System Clock and Clock Options” on page 23. 10.2.1 Pin Change Interrupt Timing An example of timing of a pin change interrupt is shown in Figure 10-1 below. |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |