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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ATtiny43U датащи(PDF) 59 Page - ATMEL Corporation |
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ATtiny43U датащи(HTML) 59 Page - ATMEL Corporation |
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59 / 182 page  59 8048B–AVR–03/09 Figure 10-1. Timing of pin change interrupts 10.3 Register Description 10.3.1 MCUCR – MCU Control Register The External Interrupt Control Register A contains control bits for interrupt sense control. • Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 External Interrupt 0 is activated by the external pin INT0 if the I-flag of SREG and the corre- sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 10-2 on page 60. Edges on INT0 are registered asynchronously. Pulses on INT0 wider than the pulse width given in Table 20-6 on page 158 will generate an interrupt. Shorter pulses are not guaranteed to gen- erate an interrupt. clk PCINT(0) pin_lat pin_sync pcint_in_(0) pcint_syn pcint_setflag PCIF PCINT(0) pin_sync pcint_syn pin_lat D Q LE pcint_setflag PCIF clk clk PCINT(0) in PCMSK(x) pcint_in_(0) 0 x Bit 765 432 10 0x35 (0x55) BODS PUD SE SM1 SM0 BODSE ISC01 ISC00 MCUCR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 |
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