ATtiny43U datasheet(110/182 Pages) ATMEL

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110

8048B–AVR–03/09

ATtiny43U

If USISIE bit in USICR and the Global Interrupt Enable Flag are set, an interrupt will be gener-

ated when this flag is set. The flag will only be cleared by writing a logical one to the USISIF bit.

Clearing this bit will release the start detection hold of USCL in two-wire mode.

A start condition interrupt will wakeup the processor from all sleep modes.

• Bit 6 – USIOIF: Counter Overflow Interrupt Flag

This flag is set (one) when the 4-bit counter overflows (i.e., at the transition from 15 to 0). If the

USIOIE bit in USICR and the Global Interrupt Enable Flag are set an interrupt will also be gener-

ated when the flag is set. The flag will only be cleared if a one is written to the USIOIF bit.

Clearing this bit will release the counter overflow hold of SCL in two-wire mode.

A counter overflow interrupt will wakeup the processor from Idle sleep mode.

• Bit 5 – USIPF: Stop Condition Flag

When two-wire mode is selected, the USIPF Flag is set (one) when a stop condition has been

detected. The flag is cleared by writing a one to this bit. Note that this is not an interrupt flag.

This signal is useful when implementing two-wire bus master arbitration.

• Bit 4 – USIDC: Data Output Collision

This bit is logical one when bit 7 in the USI Data Register differs from the physical pin value. The

flag is only valid when two-wire mode is used. This signal is useful when implementing Two-wire

bus master arbitration.

• Bits 3:0 – USICNT[3:0]: Counter Value

These bits reflect the current 4-bit counter value. The 4-bit counter value can directly be read or

written by the CPU.

The 4-bit counter increments by one for each clock generated either by the external clock edge

detector, by a Timer/Counter0 Compare Match, or by software using USICLK or USITC strobe

bits. The clock source depends on the setting of the USICS1:0 bits.

For external clock operation a special feature is added that allows the clock to be generated by

writing to the USITC strobe bit. This feature is enabled by choosing an external clock source

(USICS1 = 1) and writing a one to the USICLK bit.

Note that even when no wire mode is selected (USIWM1..0 = 0) the external clock input

(USCK/SCL) can still be used by the counter.

14.5.3

USIDR – USI Data Register

The USI Data Register can be accessed directly but a copy of the data can also be found in the

USI Buffer Register.

Depending on the USICS[1:0] bits of the USI Control Register a (left) shift operation may be per-

formed. The shift operation can be synchronised to an external clock edge, to a Timer/Counter0

Compare Match, or directly to software via the USICLK bit. If a serial clock occurs at the same

cycle the register is written, the register will contain the value written and no shift is performed.

Bit

0x0F (0x2F)

MSB

LSB

USIDR

Read/Write

R/W

Initial Value

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