ATtiny43U datasheet(102/182 Pages) ATMEL

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102

8048B–AVR–03/09

ATtiny43U

Figure 14-3. Three-wire Mode, Timing Diagram

The three-wire mode timing is shown in Figure 14-3 At the top of the figure is a USCK cycle ref-

erence. One bit is shifted into the USI Data Register (USIDR) for each of these cycles. The

USCK timing is shown for both external clock modes. In external clock mode 0 (USICS0 = 0), DI

is sampled at positive edges, and DO is changed (USI Data Register is shifted by one) at nega-

tive edges. In external clock mode 1 (USICS0 = 1) the opposite edges with respect to mode 0

are used. In other words, data is sampled at negative and output is changed at positive edges.

The USI clock modes corresponds to the SPI data mode 0 and 1.

Referring to the timing diagram (Figure 14-3), a bus transfer involves the following steps:

The slave and master devices set up their data outputs and, depending on the protocol

used, enable their output drivers (mark A and B). The output is set up by writing the

data to be transmitted to the USI Data Register. The output is enabled by setting the

corresponding bit in the Data Direction Register of Port A. Note that there is not a pre-

ferred order of points A and B in the figure, but both must be at least one half USCK

cycle before point C, where the data is sampled. This is in order to ensure that the data

setup requirement is satisfied. The 4-bit counter is reset to zero.

The master software generates a clock pulse by toggling the USCK line twice (C and

D). The bit values on the data input (DI) pins are sampled by the USI on the first edge

(C), and the data output is changed on the opposite edge (D). The 4-bit counter will

count both edges.

Step 2. is repeated eight times for a complete register (byte) transfer.

After eight clock pulses (i.e., 16 clock edges) the counter will overflow and indicate that

the transfer has been completed. If USI Buffer Registers are not used the data bytes

that have been transferred must now be processed before a new transfer can be initi-

ated. The overflow interrupt will wake up the processor if it is set to Idle mode.

Depending on the protocol used the slave device can now set its output to high

impedance.

14.3.2

SPI Master Operation Example

The following code demonstrates how to use the USI module as a SPI Master:

SPITransfer:

out

USIDR,r16

ldi

r16,(1<<USIOIF)

out

USISR,r16

ldi

r17,(1<<USIWM0)|(1<<USICS1)|(1<<USICLK)|(1<<USITC)

MSB

654321

LSB

654321

LSB

USCK

CYCLE ( Reference )

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