ATtiny43U datasheet(101/182 Pages) ATMEL

101 / 182 page

101

8048B–AVR–03/09

output to the opposite clock edge of the data input sampling. The serial input is always sampled

from the Data Input (DI) pin independent of the configuration.

The 4-bit counter can be both read and written via the data bus, and it can generate an overflow

interrupt. Both the USI Data Register and the counter are clocked simultaneously by the same

clock source. This allows the counter to count the number of bits received or transmitted and

generate an interrupt when the transfer is complete. Note that when an external clock source is

selected the counter counts both clock edges. This means the counter registers the number of

clock edges and not the number of data bits. The clock can be selected from three different

sources: The USCK pin, Timer/Counter0 Compare Match or from software.

The two-wire clock control unit can be configured to generate an interrupt when a start condition

has been detected on the two-wire bus. It can also be set to generate wait states by holding the

clock pin low after a start condition is detected, or after the counter overflows.

14.3

Functional Descriptions

14.3.1

Three-wire Mode

The USI Three-wire mode is compliant to the Serial Peripheral Interface (SPI) mode 0 and 1, but

does not have the slave select (SS) pin functionality. However, this feature can be implemented

in software if necessary. Pin names used by this mode are: DI, DO, and USCK.

Figure 14-2. Three-wire Mode Operation, Simplified Diagram

Figure 14-2 shows two USI units operating in three-wire mode, one as Master and one as Slave.

The two USI Data Registers are interconnected in such way that after eight USCK clocks, the

data in each register has been interchanged. The same clock also increments the USI’s 4-bit

counter. The Counter Overflow (interrupt) Flag, or USIOIF, can therefore be used to determine

when a transfer is completed. The clock is generated by the Master device software by toggling

the USCK pin via the PORTA register or by writing a one to bit USITC bit in USICR.

SLAVE

MASTER

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

USCK

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

USCK

PORTxn

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