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7220 датащи(PDF) 156 Page - Renesas Technology Corp |
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7220 датащи(HTML) 156 Page - Renesas Technology Corp |
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156 / 303 page ![]() M37220M3-XXXSP/FP 4.5 Functional description 7220 Group User’s Manual 4-18 Fig. 4.5.8 DA n conversion register (addresses 00DE16 and 00DF16) Fig. 4.5.9 Port P3 output mode control register (address 00CD16) b7 b6 b5 b4 b3 b2 b1 b0 DA n conversion register (DAn) (n = 1 and 2) [Address 00DE16, 00DF16] B After reset R W DA n Conversion Register 0 to 5 6 Indeterminate 0 Name Functions DA conversion set bits (DAn0–DAn5) b0 b1 b2 b3 b4 b5 Fix this bit to “0.” 1 0000 00 0000 0 0 0000 0 0 111 1 1 1111 1 1 1111 11 : 1/64Vcc : 2/64Vcc : 61/64Vcc : 62/64Vcc : 63/64Vcc : 0/64Vcc 7 0 Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is “ 0.” RW R— R— 0 b7 b6 b5 b4 b3 b2 b1 b0 Port P3 output mode control register (P3S) [address 00CD16] B Name Functions After reset R W Port P3 Output Mode Control Register 0 0 : CMOS output 1 : N-channel open-drain output 0 1 0 0 4 to 7 0 P30 output structure selection bit (P30S) P31 output structure selection bit (P31S) Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” 0 : CMOS output 1 : N-channel open-drain output 2 DA1 output enable bit (DA1S) 0 : P30 input/output 1 : DA1 output 0 3 DA2 output enable bit (DA2S) 0 : P31 input/output 1 : DA2 output RW RW RW RW R— |
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