7220 datasheet(14/303 Pages) RENESAS

14 / 303 page

viii

List of figures

7220 Group User’s Manual

Fig. 5.1.10 Flowchart of CRT interrupt processing routine

(when setting multiple interrupts) .......................................................................... 5-11

Fig. 5.1.11 Flowchart of VSYNC interrupt processing routine

(when setting multiple interrupts) .......................................................................... 5-12

Fig. 5.2.1 Color register n (M37221ERSS) .............................................................................. 5-13

Fig. 5.2.2 Color register n (M37220M3-XXXSP/FP) ................................................................ 5-14

Fig. 5.2.3 Border selection register (M37220M3-XXXSP/FP) ................................................ 5-14

Fig. 5.3.1 Connection example .................................................................................................. 5-15

Fig. 5.3.2 Correction example (1) ............................................................................................. 5-15

Fig. 5.3.3 Correction example (2) ............................................................................................. 5-16

Fig. 5.3.4 E2PROM map when using ROM correction function (1) ....................................... 5-17

Fig. 5.3.5 E2PROM map when using ROM correction function (2) ....................................... 5-18

Fig. 5.3.6 General flowchart when using ROM correction function ...................................... 5-19

Fig. 5.4.1 Connection example .................................................................................................. 5-21

Fig. 5.4.2 Byte write timing ........................................................................................................ 5-22

Fig. 5.4.3 Random address read timing ................................................................................... 5-22

Fig. 5.4.4 Flowchart of write processing routine ..................................................................... 5-23

Fig. 5.4.5 Flowchart of read processing routine ...................................................................... 5-24

Fig. 5.4.6 Flowchart of data output processing routine .......................................................... 5-25

Fig. 5.5.1 Connection example .................................................................................................. 5-26

Fig. 5.5.2 Staus read timing ....................................................................................................... 5-27

Fig. 5.5.3 Byte write timing ........................................................................................................ 5-27

Fig. 5.5.4 Flowchart of write processing routine ..................................................................... 5-28

Fig. 5.5.5 Flowchart of read processing routine ...................................................................... 5-29

Fig. 5.5.6 Flowchart of data output processing routine .......................................................... 5-30

Fig. 5.5.7 Flowchart of START condition processing routine ................................................ 5-31

Fig. 5.5.8 Flowchart of STOP condition processing routine .................................................. 5-31

Fig. 5.5.9 Flowchart of bus H processing routine ................................................................... 5-31

Fig. 5.5.10 Flowchart of data input processing routine .......................................................... 5-32

Fig. 5.5.11 Flowchart of return ACK processing routine ........................................................ 5-33

Fig. 5.5.12 Flowchart of return NACK processing routine ..................................................... 5-33

Fig. 5.5.13 Flowchart of power on processing ........................................................................ 5-36

Fig. 5.5.14 Flowchart of “CH UP/DOWN key” input processing............................................ 5-37

Fig. 5.5.15 Flowchart of “picture memory switching key” input processing ......................... 5-38

Fig. 5.5.16 Status data register ................................................................................................. 5-39

Fig. 5.5.17 Map of write data register ...................................................................................... 5-41

Fig. 5.6.1 Application circuit example 1 (I2C-BUS chassis) ................................................... 5-45

Fig. 5.6.2 Application circuit example 2 (Non-BUS chassis) ................................................. 5-46

CHAPTER 6. APPENDIX

Fig. 6.3.1 Initialization of flags in PS ......................................................................................... 6-4

Fig. 6.3.2 Stack contents after PHP instruction execution ...................................................... 6-4

Fig. 6.3.3 Note when executing PLP instruction ....................................................................... 6-4

Fig. 6.3.4 Note in decimal arithmetic operation ........................................................................ 6-5

Fig. 6.3.5 Execution of BBC or BBS instruction ....................................................................... 6-5

Fig. 6.3.6 Sequence for switching an external interrupt detection edge ................................ 6-6

Fig. 6.3.7 Initialization for serial I/O ............................................................................................ 6-6

Fig. 6.3.8 Relation between timer values and their values read

(timer setting value = 2) .............................................................................................. 6-7

Fig. 6.3.9 Relation between timer values and their values read when two timers are

connected in series (timers 1 and 2 are connected, timer 1 setting value = 2,

timer 2 setting value = 1) ............................................................................................ 6-7

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