7220 datasheet(84/303 Pages) RENESAS

84 / 303 page

2-57

7220 Group User’s Manual

FUNCTIONAL DESCRIPTION

2.8 Multi-master I2C-BUS interface

Fig. 2.8.8 I2C status register

b7 b6 b5 b4 b3 b2 b1 b0

I2C status register (S1) [Address 00D916]

I2C Status Register

6, 7

b7 b6

0 : Slave recieve mode

1 : Slave transmit mode

0 : Master recieve mode

1 : Master transmit mode

Name

Functions

After reset RW

Communication mode

specification bits

(TRX, MST)

0 : Bus free

1 : Bus busy

Bus busy flag (BB)

0 : Interrupt request issued

1 : No interrupt request issued

I2C-BUS interface interrupt

request bit (PIN)

0 : Not detected

1 : Detected

Arbitration lost detecting flag

(AL) (See note)

0 : Address mismatch

1 : Address match

Slave address comparison

flag (AAS) (See note)

0 : No general call detected

1 : General call detected

General call detecting flag

(AD0) (See note)

0 : Last bit = “0 ”

1 : Last bit = “1 ”

Last receive bit (LRB)

(See note)

Note : These bits and flags can be read out, but cannnot be written.

Indeterminate R—

R—

SCL

IICIRQ

s Bit 7: Communication mode specification bit (master/slave specification bit: MST)

This bit is used for master/slave specification for data communication. When this bit is “0,” the

slave is specified, so that a START condition and a STOP condition generated by the master are

received, and data communication is performed in synchronization with the clock generated by the

master. When this bit is “1,” the master is specified and a START condition and a STOP condition

are generated, and also the clocks required for data communication are generated on the SCL.

The MST bit is cleared to “0” in one of the following conditions.

• Immediately after completion of 1-byte data transmission when arbitration lost is detected

• When a STOP condition is detected.

• When occurrence of a START condition is disabled by the START condition duplication preventing

function (Note).

• At reset

Figure 2.8.7 shows the interrupt request signal generating timing, Figure 2.8.8 shows the I2C status

Note: The START condition duplication prevention function disables the START condition generation,

reset of bit counter reset, and SCL output when the following condition is satisfied:

a START condition is set by another master device.

Fig. 2.8.7 Interrupt request signal generating timing

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