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7220 датащи(PDF) 77 Page - Renesas Technology Corp

номер детали 7220
подробное описание детали  8-BIT SINGLE-CHIP MICROCOMPUTER
PDF  303 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

7220 датащи(HTML) 77 Page - Renesas Technology Corp

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7220 Group User’s Manual
FUNCTIONAL DESCRIPTION
2.8 Multi-master I2C-BUS interface
(2)
I2C address register (S0D: address 00D816)
The I2C address register (address 00D816) consists of a 7-bit slave address and a read/write bit. In
the addressing mode, the slave address written in this register is compared with the address data
to be received immediately after the START condition are detected.
s Bit 0: Read/write bit (RBW)
Not used when comparing addresses, in the 7-bit addressing mode. In the 10-bit addressing mode,
the first address data to be received is compared with the contents (SAD6 to SAD0 + RBW) of the
I2C address register.
The RBW bit is cleared to “0” automatically when the stop condition is detected.
s Bits 1 to 7: Slave address (SAD0–SAD6)
These bits store slave addresses. Regardless of the 7-bit addressing mode and the 10-bit addressing
mode, the address data transmitted from the master is compared with the contents of these bits.
Figure 2.8.3 shows the I2C address register.
Fig. 2.8.3 I2C address register
b7 b6 b5 b4 b3 b2 b1 b0
0
Read/write bit
(RBW)
1
to
7
Slave address
(SAD0 to SAD6)
0: Read
1: Write
0
0
The address data transmitted from
the master is compared with the
contents of these bits.
I2C Address Register
I2C address register (S0D) [Address 00D816]
B
Name
Functions
After reset RW
RW
RW



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