7220 datasheet(12/303 Pages) RENESAS

12 / 303 page

List of figures

7220 Group User’s Manual

Fig. 2.8.1 Block diagram of multi-masteer I2C-BUS interface ................................................ 2-48

Fig. 2.8.2 I2C data shift register ................................................................................................ 2-49

Fig. 2.8.3 I2C address register ................................................................................................... 2-50

Fig. 2.8.4 I2C clock control register .......................................................................................... 2-52

Fig. 2.8.5 Connection port control by BSEL0 and BSEL1 ..................................................... 2-53

Fig. 2.8.6 I2C control register ..................................................................................................... 2-54

Fig. 2.8.7 Interrupt request signal generating timing .............................................................. 2-57

Fig. 2.8.8 I2C status register ...................................................................................................... 2-57

Fig. 2.8.9 START condition generation timing diagram ........................................................ 2-58

Fig. 2.8.10 STOP condition generation timing diagram ........................................................ 2-58

Fig. 2.8.11 START condition/STOP condition detect timing diagram ................................... 2-59

Fig. 2.8.12 Address data communication format ................................................................... 2-60

Fig. 2.9.1 A-D comparator block diagram ................................................................................ 2-61

Fig. 2.9.2 A-D control register 1 (address 00EE16) ................................................................. 2-62

Fig. 2.9.3 A-D control register 2 (address 00EF16) ................................................................. 2-62

Fig. 2.10.1 14-bit PWM (DA) block diagram ............................................................................ 2-63

Fig. 2.10.2 8-bit PWM block diagram ....................................................................................... 2-64

Fig. 2.10.3 14-bit PWM output example (f(XIN) = 8 MHz) ...................................................... 2-66

Fig. 2.10.4 Pulse waveforms corresponding to weight of each bit of 8-bit PWM register 2-68

Fig. 2.10.5 Example of 8-bit PWM output ................................................................................ 2-68

Fig. 2.10.6 PWM output control register 1 (address 00D516) ................................................ 2-69

Fig. 2.10.7 PWM output control register 2 (address 00D616) ................................................ 2-70

Fig. 2.11.1 Structure of CRT display character ....................................................................... 2-71

Fig. 2.11.2 CRT display circuit block diagram ......................................................................... 2-72

Fig. 2.11.3 CRT control register (address 00EA16) ................................................................. 2-73

Fig. 2.11.4 Count method of synchronous signal .................................................................... 2-74

Fig. 2.11.5 Display position ........................................................................................................ 2-75

Fig. 2.11.6 Vertical position register n (addresses 00E116 and 00E216) ............................... 2-76

Fig. 2.11.7 Horizontal position register (address 00E016) ....................................................... 2-76

Fig. 2.11.8 Character size register (address 00E416) ............................................................. 2-77

Fig. 2.11.9 Display start position (horizontal direction) for each character size ................. 2-77

Fig. 2.11.10 Example of display character data storing form ................................................ 2-78

Fig. 2.11.11 Structure of CRT display RAM ............................................................................ 2-81

Fig. 2.11.12 Color register n (addresses 00E616 to 00E916) .................................................. 2-82

Fig. 2.11.13 Generation timing of CRT interrupt request ....................................................... 2-84

Fig. 2.11.14 Display state of blocks and occurrence of CRT interrupt request .................. 2-84

Fig. 2.11.15 Border example ...................................................................................................... 2-85

Fig. 2.11.16 Border selection register (address 00E516) ........................................................ 2-85

Fig. 2.11.17 CRT port control register (address 00EC16) ....................................................... 2-86

Fig. 2.11.18 MUTE signal output example ............................................................................... 2-87

Fig. 2.11.19 CRT clock selection register ................................................................................ 2-88

Fig. 2.12.1 ROM correction address registers ......................................................................... 2-89

Fig. 2.12.2 ROM correction enable register ............................................................................. 2-89

Fig. 2.13.1 Sequence at detecting software runaway detection ............................................ 2-90

Fig. 2.14.1 Oscillation stabilizing time at return by reset input............................................. 2-92

Fig. 2.14.2 Execution sequence example at return by occurrence of INT0 interrupt

request ...................................................................................................................... 2-92

Fig. 2.14.3 Reset input time ....................................................................................................... 2-93

Fig. 2.14.4 State transitions of low-power dissipation mode ................................................. 2-94

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