| поискавой системы для электроныых деталей |
|
7220 датащи(PDF) 70 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
7220 датащи(HTML) 70 Page - Renesas Technology Corp |
|
70 / 303 page ![]() 2-43 7220 Group User’s Manual FUNCTIONAL DESCRIPTION 2.7 Serial I/O 2.7.5 Serial I/O data receive method (when an internal clock is selected) (1) Initialization First, set the serial I/O mode register (address 00DC16) as follows. Select the synchronous clock (SM2 = “1,” SM1, SM0). Set P20 as pin SCLK (SM3 = “1”). Pin P21/SOUT is not used when receiving serial data. However, since the serial I/O port selection bit (SM3) is also used for setting pin SOUT, port P21 is automatically set as pin SOUT and loses its general-purpose I/O port function. Select the serial input pin by the serial input pin selection bit (SM6). When SM6 = “0,” signal is input from pin P22/SIN; when SM6 = “1,” signal is input from pin P21/SOUT. When pin P22/SIN is a input pin, set the port P2 direction register to input mode (“0”). For pins P20/SCLK and P21/SOUT, the corresponding bits of the port P2 direction register are automatically set by setting the serial I/O mode register. (2) Receive enable state After the above setting have been made, write “FF16” to the serial I/O register (address 00DD16). The serial I/O counter is then set to “0716” during the write cycle and receive is enabled. (3) Receive operation The data from the serial I/O data input pins (SOUT or SIN) is received one bit at a time into the serial I/O register in synchronization with rising edges of the transfer clock. Receive operation is performed according to bit 5 (SM5) of the serial I/O mode register: When SM5 is set to “0,” data is received from MSB (bit 7) of the register and shifted to the right (to low-order bit) every time new data is received. When SM5 is set to “1,” data is received from LSB (bit 0) of the register and shifted to the left (to high-order bit) every time new data is received. When all 8-bit data have been received, the serial I/O interrupt request bit (bit 2) of the interrupt request register 2 (address 00FD16) is set to “1.” Fig. 2.7.4 Serial I/O register when receiving (when SM5 = “0”) Transfer clock Serial I/O register MSB LSB D0 D1 D0 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 When receiving Note: To start receiving, set “FF16” to the serial I/O register. • • • |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |