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7220 датащи(PDF) 79 Page - Renesas Technology Corp |
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7220 датащи(HTML) 79 Page - Renesas Technology Corp |
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79 / 303 page ![]() 2-52 7220 Group User’s Manual FUNCTIONAL DESCRIPTION 2.8 Multi-master I2C-BUS interface Fig. 2.8.4 I2C clock control register b7 b6 b5 b4 b3 b2 b1 b0 I2C clock control register (S2 : address 00DB 16) I2C Clock Control Register 0 to 4 SCL frequency control bits (CCR0 to CCR4) 7 5 6 SCL mode specification bit (FAST MODE) 0 : Standard clock mode 1 : High-speed clock mode 0 Standard clock mode B Name Functions After reset RW 0 0 0 ACK bit (ACK BIT) ACK clock bit (ACK) 0 : ACK is returned. 1 : ACK is not returned. 0 : No ACK clock 1 : ACK clock High speed clock mode Setup disabled Setup disabled 00 to 02 Setup disabled 333 03 Setup disabled 250 04 100 400 (See note) 05 83.3 166 06 500/CCR value 1000/CCR value 17.2 34.5 1D 16.6 33.3 1E 16.1 32.3 1F (at φ = 4 MHz, unit : kHz) Note: At 4000kHz in the high-speed clock mode, the duty is as below . “0” period : “1” period = 3 : 2 In the other cases, the duty is as below. “0” period : “1” period = 1 : 1 Setup value of CCR4–CCR0 RW RW RW RW |
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