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7220 датащи(PDF) 56 Page - Renesas Technology Corp |
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7220 датащи(HTML) 56 Page - Renesas Technology Corp |
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56 / 303 page ![]() 2-29 7220 Group User’s Manual FUNCTIONAL DESCRIPTION 2.5 Interrupts 2.5.2 Interrupt control Each interrupt can be controlled with the interrupt request bit, the interrupt control bit, and the interrupt disable flag. Reset Interrupt enable bit Interrupt disable flag (I) Start of interrupt process Interrupt request bit BRK instruction Fig. 2.5.2 Interrupt control logic (1) Interrupt request bit When an interrupt request occurs, the corresponding bit of the interrupt request register is set to “1.” The interrupt request is held active until an interrupt is accepted or “0” is written to the relevant bit by software. The bit is automatically cleared to “0” simultaneously when the interrupt is accepted. Interrupt request bits are cleared to “0” (to clear the interrupt request) by software but are not set to “1” (to generate the interrupt request) by software. Each interrupt request bit is assigned to interrupt request registers 1 and 2 (addresses 00FC16 and 00FD16). (2) Interrupt enable bit Interrupt enable bits control the acceptance of each interrupt. When the interrupt enable bit is cleared to “0” (to disable an interrupt), the interrupt cannot be accepted. Conversely, when the interrupt enable bit is set to “1” (to enable an interrupt), the interrupt is accepted. However, if the interrupt disable flag is set to “1,” the interrupt cannot be accepted even when the interrupt enable bit is set to “1.” Each interrupt enable bit is assigned to interrupt control registers 1 and 2 (addresses 00FE16 and 00FF16). (3) Interrupt disable flag (I) The interrupt disable flag (I) is assigned to bit 2 of the processor status register. When the interrupt disable flag is set to “1,” all interrupts except the BRK instruction interrupt are disabled; when the flag is cleared to “0,” interrupts are enabled. However, if the interrupt disable flag is cleared to “0,” the interrupt cannot be accepted even when the interrupt enable bit is “0.” |
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