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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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7220 датащи(PDF) 74 Page - Renesas Technology Corp |
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7220 датащи(HTML) 74 Page - Renesas Technology Corp |
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74 / 303 page  2-47 7220 Group User’s Manual FUNCTIONAL DESCRIPTION 2.8 Multi-master I2C-BUS interface 2.8 Multi-master I2C-BUS interface The multi-master I2C-BUS interface is a serial communications circuit, conforming to the Philips I2C-BUS data transfer format. This interface, offering both an arbitration lost detection and a synchronous functions, is useful for the multi-master serial communications. Figure 2.8.1 shows a block diagram of the multi-master I2C-BUS interface and Table 2.8.1 shows multi- master I2C-BUS interface functions. The M37220M3-XXSP/FP does not have this function. Table 2.8.1 Multi-master I2C-BUS interface functions Item Format Communication mode SCL clock frequency Function In conformity with Philips I2C-BUS standard: 10-bit addressing format 7-bit addressing format High-speed clock mode Standard clock mode In conformity with Philips I2C-BUS standard: Master transmission Master reception Slave transmission Slave reception 16.1 kHz to 400 kHz (at f = 4 MHz) f: System clock = f(X IN )/2 Note: We are not responsible for any third party’s infringement of patent rights or other rights attributable to the use of the control function (bits 6 and 7 of the I2C control register at address 00DA16) for connections between the I2C-BUS interface and ports (SCL1, SCL2, SDA1, SDA2). |
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