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7220 Group User’s Manual

FUNCTIONAL DESCRIPTION

2.8 Multi-master I2C-BUS interface

(5)

I2C status register (S1: address 00D916)

The I2C status register (address 00D916) controls the I2C-BUS interface status. The low-order 4 bits

are read-only bits and the high-order 4 bits can be read out and written to.

s Bit 0: Last receive bit (LRB)

This bit stores the last bit value of received data and can also be used for ACK receive confirmation.

If ACK is returned when an ACK clock occurs, the LRB bit is set to “0.” If ACK is not returned,

this bit is set to “1.” Except in the ACK mode, the last bit value of received data is input. The state

of this bit is changed from “1” to “0” by executing a write instruction to the I2C data shift register

(address 00D716).

s Bit 1: General call detecting flag (AD0)

This bit is set to “1” when a general callV whose address data is all “0” is received in the slave

mode. By a general call of the master device, every slave device receives control data after the

general call. The AD0 bit is set to “0” by detecting the STOP condition or START condition.

s Bit 2: Slave address comparison flag (AAS)

This flag indicates a comparison result of address data.

In the slave receive mode, when the 7-bit addressing format is selected, this bit is set to “1” in

one of the following conditions.

• The address data immediately after occurrence of a START condition matches the slave address

stored in the high-order 7 bits of the I2C address register (address 00D816).

• A general call is received.

In the slave reception mode, when the 10-bit addressing format is selected, this bit is set to “1”

with the following condition.

• When the address data is compared with the I2C address register (8 bits consists of slave

address and RBW), the first bytes match.

The state of this bit is changed from “1” to “0” by executing a write instruction to the I2C data

shift register (address 00D716).

s Bit 3: Arbitration lostV detecting flag (AL)

In the master transmission mode, when a device other than the microcomputer sets the SDA to

LOW by any other device, arbitration is judged to have been lost, so that this bit is set to “1.” At

the same time, the TRX bit is set to “0,” so that immediately after transmission of the byte, whose

arbitration was lost is completed, the MST bit is set to “0.” When arbitration is lost during slave

address transmission, the TRX bit is set to “0” and the reception mode is set. Consequently, it

becomes possible to receive and recognize its own slave address transmitted by another master

device.

VArbitration lost: The status in which communication as a master is disabled.

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