7220 datasheet(46/303 Pages) RENESAS

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2-19

7220 Group User’s Manual

2.3 Memory assignment

FUNCTIONAL DESCRIPTION

2.3.11 Timer mode registers (address 00F416 and 00F516)

The timer 12 mode register is assigned to address 00F416 and the timer 34 mode register is assigned to

address 00F516. Both registers consist of 8 bits. They select the count source of timer and control the count

stop bit. Bits 5 to 7 of the timer 12 mode register and bits 6, 7 of the timer 34 mode register are not used.

2.3.12 CPU mode register (address 00FB16)

The CPU mode register is assigned to address 00FB16. This register consists of 8 bits, and specifies the

stack page. Set bits 0 and 1 are set to “0,” and set bits 3 to 7 to “0.”

2.3.13 Interrupt request registers (addresses 00FC16 and 00FD16)

The interrupt request register 1 is assigned to address 00FC16 and the interrupt request register 2 is

assigned to address 00FD16. Both registers consist of 8 bits, and hold content of each interrupt request bit.

Bits 3 and 5 to 7 of the interrupt request register 2 are not used.

2.3.14 Interrupt control registers (addresses 00FE16 and 00FF16)

The interrupt control register 1 is assigned to address 00FE16 and the interrupt control register 2 is assigned

to address 00FF16. Both registers consist of 8 bits, and sets enable/disable of interrupts.

Bits 7 to 5 and 3 of the interrupt control register 2 are not used.

2.3.15 2 page register (addresses 021716 to 021B16) (only M37221M8-XXXSP and M37221MA-XXXSP)

(1)

ROM correction addresses (address 021716 to 021A16)

Addresses 021716 to 021A16 are assigned to ROM correction address. The ROM data addresses to

be corrected are set to the ROM correction addresses.

(2)

ROM correction enable register (address 021B16)

The ROM correction enable register is assigned to address 021B16. This register consist of 8 bits,

and controls the ROM correction function. Bits 2 to 7 are not used.

2.3.16 CRT display RAM (addresses 060016 to 06B716)

The display RAM is used to specify the character to be displayed on the CRT and its color. Two addresses

are used for one character: one address (8 bits) to specify each character code and the other (8 bits) to

specify the color of the character.

2.3.17 ROM (addresses A00016 to FFFF16)

The mask ROM is assigned.

In this internal ROM, addresses FFDE16, FFDF16, FFE416, FFF516, and FFF816 to FFFF16 are assigned to

vector area for reset and for interrupts. A vector jump destination storage address (16 bits) are stored in

2 addresses by the 1 interrupt source.

2.3.18 CRT display ROM (addresses 1000016 to 11FFF16)

The display ROM stores (masks) character patterns of each character to be displayed on the CRT. Although

one character consists of 16 (vertical)

× 12 (horizontal) dots, it is divided into a 16 × 8 dot and a 16 × 4

dot pattern, with each pattern stored in one address. In other words, two addresses (16 bits) are used for

one character. The ROM can store up to 256 kinds of characters.

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